Howard Mao
04383a31f5
Revert "make sure L2MetadataArray assigns unoccupied way if available"
...
This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
2015-11-21 10:35:40 -08:00
Howard Mao
3c95afebc6
Shift set index for multi-bank configurations
...
Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
2015-11-20 23:24:57 -08:00
Howard Mao
55a85cc67a
make sure wmask is passed for PutBlock in broadcast hub
2015-11-20 14:09:24 -08:00
Howard Mao
941b64cd62
make partial write-masking PutBlock constructor always set alloc bit
2015-11-20 13:34:07 -08:00
Howard Mao
24f7b9f472
make sure L2MetadataArray assigns unoccupied way if available
2015-11-19 10:45:54 -08:00
Howard Mao
e50c7ad306
add NASTI error assertions back in
2015-11-18 17:05:54 -08:00
Henry Cook
2b977325e3
Make prefetch type available in a_type, issue probeInvalidates for putPrefetches
2015-11-16 23:26:13 -08:00
Andrew Waterman
d426ecee78
Remove IPI network
...
This is now provided via MMIO.
2015-11-16 21:52:24 -08:00
Henry Cook
0290635454
amo_shift_bits -> amo_shift_bytes
2015-11-16 19:07:58 -08:00
Henry Cook
64aaf71b06
L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type.
...
Transaction metadata for primary and seconday misses now stored in the secondary miss queue.
Added BuiltInAcquireBuilder factory.
2015-11-16 18:10:09 -08:00
Henry Cook
03fa06e6e7
fix prefetch lockup on L2 hit
2015-11-15 12:51:34 -08:00
Howard Mao
e12efab423
skip meta_write state if no meta write pending
2015-11-13 13:50:35 -08:00
Howard Mao
7e7d688a01
make sure L2 passes no-alloc acquires through to outer memory
2015-11-12 15:40:58 -08:00
Howard Mao
b3865c370a
make sure correct addr_beat is sent for Get response by narrower/converter
2015-11-12 15:40:38 -08:00
Howard Mao
f397d61033
add alloc option to Put constructor
2015-11-12 11:39:59 -08:00
Howard Mao
7733fbe6a3
make sure no-alloc write still updates data array if there is a cache hit
2015-11-12 11:39:36 -08:00
Howard Mao
b59ce5fed4
make sure L2 waits for outer grant before sending grant for write request
2015-11-10 16:06:14 -08:00
Howard Mao
42d3d09d7a
add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer
2015-11-09 11:49:19 -08:00
Howard Mao
7942be4e01
make sure outerTL method is idempotent
2015-11-09 11:10:02 -08:00
Henry Cook
e3efc09b5b
remove unnecessary UInt encode/decode on releaseMatches path
2015-11-05 17:20:03 -08:00
Henry Cook
3698153535
OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank
2015-11-03 14:31:35 -08:00
Howard Mao
baa2544651
Fix some more issues with narrower
2015-10-31 19:36:30 -07:00
Howard Mao
812c5bcc55
make sure narrower can handle sub-block level requests correctly
2015-10-31 15:58:36 -07:00
Howard Mao
d4b8653002
fix too strict assertion in broadcast hub
2015-10-31 15:58:10 -07:00
Howard Mao
c10870a87c
make sure ID width requirement in TL -> NASTI converter is correct
2015-10-27 13:25:29 -07:00
Howard Mao
9fa4541916
get rid of unused full signal in ReorderQueue
2015-10-26 12:17:25 -07:00
Howard Mao
6403f27fbe
fix bug in ReorderQueue breaking TileLink Unwrapper
2015-10-22 15:52:55 -07:00
Henry Cook
f8594da1d3
depend on external cde library
2015-10-21 18:17:17 -07:00
Howard Mao
02d113b39f
outerDataBits / innerDataBits should be per beat, not per block
2015-10-21 11:31:13 -07:00
Howard Mao
baf95533a4
fix combinational loop in TileLink Unwrapper
2015-10-20 23:26:11 -07:00
Howard Mao
ffe7df2fed
make sure TL -> NASTI converter acquire ready not dependent on valid
2015-10-20 22:09:22 -07:00
Howard Mao
1c135c1628
fix ready-valid mixup in TileLink unwrapper
2015-10-20 21:07:42 -07:00
Henry Cook
4389b9edb0
tilelink parameter tweak: addrBits now a constant
2015-10-20 15:00:30 -07:00
Howard Mao
d12403e7dc
fix up and simplify TL -> NASTI converter logic
2015-10-19 13:47:13 -07:00
Henry Cook
d391f97953
Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU.
2015-10-16 19:11:06 -07:00
Henry Cook
e1f573918d
simplify TileLinkParameters with Option
2015-10-16 18:24:38 -07:00
Howard Mao
49667aa4b0
make sure broadcast acquire tracker doesn't try to send requests back-to-back
2015-10-14 18:56:13 -07:00
Howard Mao
1d362d6d3a
make sure correct parameters are used for TileLink constructors
2015-10-14 17:58:54 -07:00
Henry Cook
7fa3eb95e3
refactor tilelink params
2015-10-14 12:13:37 -07:00
Henry Cook
66ea39638e
GlobalAddrMap
2015-10-14 00:23:28 -07:00
Henry Cook
31be6407ec
Removed all traces of params
2015-10-14 00:23:28 -07:00
Henry Cook
908922c1a4
refactor NASTI to not use param
2015-10-14 00:23:28 -07:00
Howard Mao
47da284e56
TileLinkNarrower should do nothing if interfaces are the same width
2015-10-13 13:28:47 -07:00
Howard Mao
83df05cb6a
add TileLink data narrower
2015-10-13 12:45:39 -07:00
Howard Mao
993ed86198
move ReorderQueue to utils.scala
2015-10-13 09:49:22 -07:00
Andrew Waterman
0fe16ac1c0
Chisel3 compatibility fixes
2015-09-30 14:37:00 -07:00
Howard Mao
1e7f656527
get release block address from inner release
2015-09-28 15:02:51 -07:00
Andrew Waterman
3b1da4c57e
Revert "replace remaining uses of Vec.fill"
...
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
2015-09-25 17:06:57 -07:00
Andrew Waterman
20b7a82ab6
Use Vec.fill, not Vec.apply, when making Vec literals
2015-09-25 17:06:52 -07:00
Andrew Waterman
2179cb64ae
Let isRead be true for store-conditional
...
This works around a deadlock bug in the L1 D$, and is arguably true.
2015-09-25 15:28:02 -07:00
Howard Mao
308022210a
use updated NASTI channel constructors
2015-09-25 12:07:27 -07:00
Howard Mao
8c4ac0f4f3
make sure CSR/SCR data width matches xLen
2015-09-25 12:07:03 -07:00
Howard Mao
d1f2d40a90
replace remaining uses of Vec.fill
2015-09-24 17:50:09 -07:00
Howard Mao
3ff830e118
ReorderQueue uses Vec of Bools instead of Bits for roq_free
2015-09-24 17:43:53 -07:00
Howard Mao
83740dfaa5
Merge branch 'master' of github.com:ucb-bar/uncore
2015-09-24 17:10:09 -07:00
Howard Mao
3b86790c3f
replace NASTIMasterIO and NASTISlaveIO with NASTIIO
2015-09-24 16:58:20 -07:00
ducky
ee6754daca
Fix clone -> cloneType
2015-09-24 16:18:25 -07:00
Howard Mao
b4d21148ec
get rid of NASTI error assertion
2015-09-22 09:43:42 -07:00
Howard Mao
8b2341b1b1
use reorder queue instead of extra tag bit to determine TL g_type in NASTI -> TL converter
2015-09-18 09:41:37 -07:00
Howard Mao
bd536d8832
make HTIFModuleIO an anonymous bundle
2015-09-14 12:58:44 -07:00
Howard Mao
9d89d2a558
get rid of MemIO -> TileLink converters
2015-09-14 12:58:44 -07:00
Howard Mao
f9965648f2
fix up some things in tilelink.scala
2015-09-14 12:57:54 -07:00
Howard Mao
64717706a9
get rid of non-NASTI RTC module
2015-09-14 12:57:54 -07:00
Howard Mao
6ee6ea4f1e
use Put/Get/PutBlock/GetBlock constructors in broadcast hub
2015-09-14 12:57:54 -07:00
Howard Mao
ae3d96013a
make TL -> NASTI converter ingest ClientUncachedTileLinkIO and move functionality to Unwrapper
2015-09-14 12:57:54 -07:00
Howard Mao
21f96f382c
split off SCR functionality from HTIF
2015-09-14 12:57:54 -07:00
Howard Mao
bdc6972a8d
separate RTC updates from HTIF
2015-09-14 12:56:44 -07:00
Howard Mao
24f3fac90a
fix broadcast hub and TL -> NASTI converter to support subblock operations
2015-09-14 12:56:44 -07:00
Andrew Waterman
24389a5257
Chisel3 compatibility fixes
2015-09-11 15:41:39 -07:00
Andrew Waterman
350d530766
Use Vec.fill, not Vec.apply, for Vec literals
2015-08-27 10:00:43 -07:00
Andrew Waterman
94287fed90
Avoid type-unsafe assignments
2015-08-27 09:57:36 -07:00
Andrew Waterman
05d311c517
Use Vec.apply, not Vec.fill, for type nodes
2015-08-27 09:47:02 -07:00
Henry Cook
005752e2a6
use the parameters used to create the original object
2015-08-10 14:43:17 -07:00
Andrew Waterman
01fc61ba96
Don't construct so many Vecs
2015-08-05 18:43:59 -07:00
Howard Mao
a551a12d70
add missing Wire wrap in BasicCrossbar
2015-08-05 17:05:31 -07:00
Andrew Waterman
eb6583d607
use cloneType in PhysicalNetworkIO
2015-08-05 16:47:49 -07:00
Andrew Waterman
798ddeb5f5
Chisel3 compatibility: use >>Int instead of >>UInt
...
The latter doesn't contract widths anymore.
2015-08-04 13:15:17 -07:00
Andrew Waterman
77cf26aeba
Chisel3: Flip order of := and <>
2015-08-03 18:53:39 -07:00
Andrew Waterman
121e4fb511
Flip direction of some bulk connects
2015-08-03 18:01:14 -07:00
Andrew Waterman
a21979a2fa
Bits -> UInt
2015-08-03 18:01:06 -07:00
Andrew Waterman
9c7a41e8d3
Chisel3: bulk connect is not commutative
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We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:09:00 -07:00
Andrew Waterman
6fc807f069
Chisel3: Avoid subword assignment
2015-08-01 21:08:35 -07:00
Andrew Waterman
6d574f8c1b
Fix incompatible assignment
2015-07-31 00:59:34 -07:00
Andrew Waterman
377e17e811
Add Wire() wrap
2015-07-31 00:32:02 -07:00
Andrew Waterman
0686bdbe28
Avoid cross-module references
...
You can't instantiate a Vec in one module and use it in another.
An idiosyncrasy of the Chisel2 implementation let this one slip by.
In this case, it's just a matter of using def instead of val.
2015-07-30 23:49:06 -07:00
Andrew Waterman
8f7b390353
UInt-> Bits; avoid mixed UInt/SInt code
2015-07-30 23:49:06 -07:00
Andrew Waterman
6c391e3b37
Use UInt(0), not UInt(width=0), for constant 0
2015-07-30 23:49:06 -07:00
Henry Cook
c70b495f6d
moved buses to junctions repo
2015-07-29 18:04:30 -07:00
Andrew Waterman
a69c749249
Fix compilation with scala 2.11.6
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We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
2015-07-28 16:24:45 -07:00
Andrew Waterman
f8ec6d6393
Chisel3 compatibility: use BitPat for don't-cares
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Also, call the UInt factory instead of the Bits one, for good measure.
2015-07-28 02:46:23 -07:00
Andrew Waterman
0e06c941df
Chisel3 compatibility fixes
2015-07-23 14:58:46 -07:00
Andrew Waterman
3c0475e08b
Add Wire() wrap
2015-07-15 20:24:03 -07:00
Andrew Waterman
2d6b3b2331
Don't use clone
2015-07-15 18:06:27 -07:00
Andrew Waterman
276f53b652
Delete BigMem; it's not used anymore
2015-07-15 17:41:47 -07:00
Andrew Waterman
15cec0eab7
Vec(Reg) -> Reg(Vec)
2015-07-15 12:44:54 -07:00
Andrew Waterman
e76a9d3493
Chisel3: Don't mix Mux types
2015-07-11 14:05:39 -07:00
Andrew Waterman
5dc3da008e
Use Chisel3 SeqMem construct
2015-07-11 13:36:26 -07:00
Henry Cook
fb91e3e1ab
minor metadata API update (0.3.3)
2015-07-09 14:36:09 -07:00
Andrew Waterman
55059632c4
Temporarily use HTIF to push RTC value to cores
2015-07-05 16:19:39 -07:00
Henry Cook
d7cb60e8fa
L2 WritebackUnit bug fix
2015-07-02 13:52:40 -07:00
Andrew Waterman
b4e38192a1
Fix (?) L2$ miss bug
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The victim's metadata was incorrectly used for the new line.
2015-06-24 18:01:56 -07:00
Andrew Waterman
ea76800d1a
Fix data array reset bug
...
io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.
This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon. It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
2015-06-11 15:28:23 -07:00
Henry Cook
f3a838cedf
nasti converters, hub bugfix
2015-05-21 19:49:17 -07:00
Henry Cook
c202449e34
first version NASTI IOs
2015-05-14 15:29:49 -07:00
Henry Cook
90c9ee7b04
fix unalloc putblocks
2015-05-14 12:37:35 -07:00
Henry Cook
a7fa77c7fc
track operand size for Gets
2015-05-13 23:28:18 -07:00
Henry Cook
172c372d3e
L2 alloc cleanup
2015-05-12 17:14:06 -07:00
Henry Cook
90ced93eeb
Merge branch 'master' into gh-pages
2015-05-07 12:35:14 -07:00
Henry Cook
4cef8c9cd4
Added MemIOArbiter
2015-05-07 10:55:38 -07:00
Henry Cook
1e05fc0525
First pages commit
2015-04-29 13:18:26 -07:00
Henry Cook
3673295d03
network shim cleanup
2015-04-27 16:59:30 -07:00
Henry Cook
09e30041ed
Voluntary Writeback tracker rewrite
2015-04-27 12:56:33 -07:00
Henry Cook
11b5222d01
Refactored WritebackUnit
2015-04-21 22:23:04 -07:00
Henry Cook
4c7969b2b3
Metadata docs and api cleanup
2015-04-20 16:32:09 -07:00
Henry Cook
f66a9fd7a6
simplify ClientMetadata.makeRelease
2015-04-20 10:46:02 -07:00
Henry Cook
6d40a61060
TileLink scala doc and parameter renaming
2015-04-19 22:06:44 -07:00
Henry Cook
ba7a8b1752
TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
2015-04-17 16:55:20 -07:00
Henry Cook
ce3271aef2
refactor LNClients and LNManagers
2015-04-15 15:48:36 -07:00
Henry Cook
90f800d87d
Grant bugfixes and more comments
2015-04-13 15:57:06 -07:00
Henry Cook
3cf1778c92
moved ecc lib to uncore, l2 checks for partial write masks when ecc is enabled
2015-04-06 12:22:23 -07:00
Henry Cook
9708d25dff
Restructure L2 state machine and utilize HeaderlessTileLinkIO
2015-04-06 12:19:51 -07:00
Henry Cook
ced627f00a
slight mod to pending_puts
...
cleaner state transition logic
2015-04-01 15:24:53 -07:00
Andrew Waterman
c941f0a68e
New virtual memory implementation (Sv39)
2015-03-27 16:21:29 -07:00
Henry Cook
8959b2e81a
TileLinkEnqueuer
2015-03-26 13:29:52 -07:00
Henry Cook
b7af610569
broadcast hub bugfix
2015-03-26 11:29:04 -07:00
Henry Cook
4176edaa34
clean up tracker allocation
2015-03-26 10:17:51 -07:00
Henry Cook
db5511300d
Merge branch 'l2-subblock-merging'
2015-03-18 23:52:06 -07:00
Henry Cook
3cf033180f
pending read fix
2015-03-18 22:41:09 -07:00
Henry Cook
004ad11af6
cleanup pending signals
2015-03-18 22:14:41 -07:00
Henry Cook
002851f836
disentangle is_hit logic
2015-03-18 21:11:40 -07:00
Henry Cook
b92ea60891
you can 'hit' with putblocks even when the tag doesn't match but you still better writeback
2015-03-18 19:32:46 -07:00
Henry Cook
fb8071c12d
generous hit detection on PutBlocks
2015-03-18 18:49:32 -07:00
Henry Cook
19059bf0eb
put data can be used for ignts
2015-03-18 18:28:03 -07:00
Henry Cook
1ff184bf62
first cut at optimized state transitions
2015-03-18 17:55:05 -07:00
Henry Cook
e325399c87
Re-split mem resp tag and data queues
2015-03-18 12:49:53 -07:00
Henry Cook
42aa4aa8ca
Secondary miss param
2015-03-17 22:53:50 -07:00
Henry Cook
b364d387de
Merge branch 'l2-subblock-merging' of github.com:ucb-bar/uncore into l2-subblock-merging
2015-03-17 22:46:54 -07:00
Henry Cook
825c4b2850
make ignts more eager
2015-03-17 22:44:53 -07:00
Yunsup Lee
aa5435800d
fix get merging, and always turn it on
2015-03-17 22:43:00 -07:00
Yunsup Lee
f4f59464df
fix pending_puts initialization
2015-03-17 21:44:26 -07:00
Henry Cook
0e4cf74d8a
always merge Puts
2015-03-17 20:53:27 -07:00
Henry Cook
d48775eecb
cleanup outdated comments
2015-03-17 20:31:23 -07:00
Henry Cook
638bace858
avoid reading data when write mask is full
2015-03-17 20:28:21 -07:00
Henry Cook
b9591b297c
added s_wait_puts to L2AcquireTracker
2015-03-17 20:28:21 -07:00
Henry Cook
2d3f947a9c
cleaned up finish counter
2015-03-17 20:28:21 -07:00
Yunsup Lee
9de5161d7a
guard all writes to data ram with masks
2015-03-17 20:24:04 -07:00
Yunsup Lee
d14efce0b4
fix wmask_buffer initialization
2015-03-17 19:54:11 -07:00
Yunsup Lee
2d7375760d
set pending_writes for puts
2015-03-17 18:35:04 -07:00
Yunsup Lee
504eedbf89
fixes in in bit manipulation
2015-03-17 18:07:52 -07:00
Henry Cook
b08dced37c
first cut at pending scoreboarding
2015-03-17 17:51:00 -07:00
Yunsup Lee
4fd01d82b8
don't block finish messages when grant'ing
2015-03-17 17:48:02 -07:00
Yunsup Lee
a52a729ab9
bugfix wmask handling
2015-03-17 15:54:21 -07:00
Henry Cook
fc0ae81a97
added finish counter
2015-03-17 15:04:30 -07:00
Henry Cook
5c2461c743
merge data wmask bugfix
2015-03-17 13:09:47 -07:00
Henry Cook
dc88614094
overlapping read/resps in l2 fix
2015-03-17 13:09:47 -07:00
Henry Cook
730a13abf2
pending read fix
2015-03-17 13:09:46 -07:00
Henry Cook
23f8033df5
turn off self probes again
2015-03-17 13:09:46 -07:00
Henry Cook
d9598d26f2
fix assert
2015-03-17 13:09:46 -07:00
Henry Cook
6d565d22e3
clean up acquire alloc in hub
2015-03-17 13:09:45 -07:00
Henry Cook
3f070eee1f
first cut of merging puts/gets
2015-03-17 13:09:44 -07:00
Henry Cook
6af48e168a
cleanup mergeData buffer
2015-03-17 13:08:14 -07:00
Henry Cook
9bedde9a8a
re-merge mem resp queues
2015-03-17 12:22:57 -07:00
Henry Cook
1471d9debc
fix assert
2015-03-17 05:40:05 -07:00
Yunsup Lee
0e51fef200
bugfix where an in-progress acquire can be blocked by another acquire tracker being free'd up in between
2015-03-17 05:37:56 -07:00
Henry Cook
ce9d4b6e70
further amo cleanups
2015-03-17 05:37:41 -07:00
Henry Cook
f35a6a574f
Add a queue on released data coming in to L2
2015-03-16 13:25:01 -07:00
Henry Cook
b72230a9f0
PutBlock bugfix
2015-03-16 00:09:55 -07:00
Henry Cook
f6d1a2fb76
No more self-probes required
2015-03-16 00:09:38 -07:00
Henry Cook
23a6b007c1
Fix BroadcastHub AcquiteTracker allocation bug and clean up tracker wiring
2015-03-15 23:10:51 -07:00
Henry Cook
c03976896e
separate queues for resp tag and data
2015-03-15 17:58:17 -07:00
Andrew Waterman
6e540825b2
Use entire 12-bit CSR address
2015-03-14 02:15:24 -07:00
Yunsup Lee
3a78ca210d
bugfix in uncached TL to TL convertors
2015-03-12 16:33:41 -07:00
Henry Cook
8181262419
clean up incoherent and probe flags
2015-03-12 16:22:14 -07:00
Henry Cook
dcc84c4dd3
arbiter probe ready bugfix
2015-03-12 16:02:51 -07:00
Yunsup Lee
2c31ed6426
previous bug fix for meta data writeback wasn't quite right
2015-03-12 15:34:20 -07:00
Yunsup Lee
5e40c8ba77
write back meta data when cache miss even when coherence meta data is clean
2015-03-12 14:36:46 -07:00
Albert Ou
8f8022379c
Fix AMO opcode extraction
2015-03-11 23:24:58 -07:00
Albert Ou
f75126c39c
Require self probes for all built-in Acquire types
...
This ensures that puts by the RoCC accelerator properly invalidates its
tile's L1 D$, with which it currently shares the same TileLink port.
2015-03-11 23:24:58 -07:00
Henry Cook
1aff919c24
added prefetchAck Grant type
2015-03-11 17:32:06 -07:00
Henry Cook
059575c334
cleanup mergeData and prep for cleaner data_buffer in L2
2015-03-11 15:43:41 -07:00
Henry Cook
b4ed1d9121
Add builtin prefetch types to TileLink
2015-03-11 14:28:17 -07:00
Yunsup Lee
3ab1aca7de
L2 subblock access bugfix
2015-03-11 01:56:47 -07:00
Henry Cook
17072a0041
L2 Writeback bugfix
2015-03-10 01:15:03 -07:00
Henry Cook
a1f04386f7
Headerless TileLinkIO and arbiters
2015-03-09 16:34:59 -07:00
Henry Cook
002f1a1b39
pin outer finish header
2015-03-09 12:40:37 -07:00
Henry Cook
df79e7ff8d
secondary miss bug
2015-03-05 15:51:18 -08:00
Henry Cook
8e41fcf6fc
reduce MemIFTag size, enable non pow2 HellaFLowQueue size
2015-03-05 15:51:02 -08:00
Henry Cook
1bed6ea498
New metadata-based coherence API
2015-02-28 17:32:03 -08:00
Henry Cook
0a8722e881
bugfix for indexing DataArray of of small L2
2015-02-17 00:37:40 -08:00
Henry Cook
0c66e70f14
cleanup of conflicts; allocation bugfix
2015-02-06 13:20:44 -08:00
Henry Cook
7b86ea17cf
rename L2HellaCache to L2HellaCacheBank
2015-02-03 19:38:01 -08:00
Stephen Twigg
3b3250339a
Explicitely convert results of Bits Muxes to UInt
...
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:15:01 -08:00
Henry Cook
6141b3efc5
uncached -> builtin_type
2015-02-02 01:02:06 -08:00
Henry Cook
e6491d351f
Offset AMOs within beat and return old value
2015-02-02 00:22:21 -08:00
Henry Cook
3aa030f960
Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
2015-02-01 20:37:16 -08:00
Henry Cook
7b4e9dd137
Block L2 transactions on the same set from proceeding in parallel
2015-02-01 20:29:23 -08:00
Henry Cook
973eb43128
state machine bug on uncached write hits
2015-02-01 20:29:23 -08:00
Henry Cook
f58f8bf385
Make L2 data array use a single Mem
2015-01-25 15:37:04 -08:00
Henry Cook
9ef00d187f
%s/master/manager/g + better comments
2014-12-29 22:55:58 -08:00
Henry Cook
e62c71203e
disconnect unused outer network headers
2014-12-22 18:50:37 -08:00
Henry Cook
2ef4357ca8
acquire allocation bugfix
2014-12-19 17:39:23 -08:00
Henry Cook
f234fe65ce
Initial verison of L2WritebackUnit, passes MiT2 bmark tests
2014-12-19 03:03:53 -08:00
Henry Cook
d121af7f94
Simplify release handling
2014-12-18 17:12:29 -08:00
Henry Cook
bfcfc3fe18
refactor cache params
2014-12-17 14:28:14 -08:00
Henry Cook
ab39cbb15d
cleanup DirectoryRepresentation and coherence params
2014-12-15 19:24:42 -08:00
Andrew Waterman
d04da83f96
Make data RAMs 1RW instead of 1R1W
2014-12-15 17:36:17 -08:00
Henry Cook
6a8b66231c
Add uncached->cached tilelink converter
2014-12-12 17:06:03 -08:00
Henry Cook
424df2368f
1R/W L2 data array?
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Add TLDataBeats to new LLC; all bmarks pass
2014-12-12 17:05:21 -08:00
Henry Cook
3026c46a9c
Finish adding TLDataBeats to uncore & hub
2014-12-12 17:04:52 -08:00
Henry Cook
2f733a60db
Begin adding TLDataBeats to uncore
2014-12-12 17:04:31 -08:00
Henry Cook
404773eb9f
fix wb bug
2014-12-03 14:22:39 -08:00
Henry Cook
05b5188ad9
meta and data bundle refactor
2014-11-19 15:55:25 -08:00
Henry Cook
a519a43f23
Merge branch 'master' into new-llc
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Conflicts:
src/main/scala/coherence.scala
src/main/scala/memserdes.scala
src/main/scala/tilelink.scala
2014-11-12 16:25:25 -08:00
Henry Cook
cb7e712599
Added uncached write data queue to coherence hub
2014-11-12 12:55:07 -08:00
Henry Cook
82155f333e
Major tilelink revision for uncached message types
2014-11-11 17:36:55 -08:00
Henry Cook
35553cc0b7
NullDirectory sharers.count fix
2014-11-11 16:05:25 -08:00
Henry Cook
10309849b7
Remove master_xact_id from Probe and Release
2014-11-06 12:07:33 -08:00
Henry Cook
27c72e5eed
nearly all isa tests pass
2014-10-23 21:50:03 -07:00
Henry Cook
a891ba1d46
more correct handling of internal state
2014-10-21 17:40:30 -07:00
Henry Cook
044b19dbc1
Compiles and elaborates, does not pass asm tests
2014-10-15 11:46:35 -07:00
Henry Cook
86bdbd6535
new tshrs, compiles but does not elaborate
2014-10-07 22:33:10 -07:00
Henry Cook
394eb38a96
temp; converted voluntary wb tracker
2014-10-03 01:06:49 -07:00
Henry Cook
dc1a61264d
initial version, acts like old hub
2014-10-03 01:06:49 -07:00
Henry Cook
d735f64110
Parameter API update
2014-10-02 16:47:35 -07:00
Henry Cook
7571695320
Removed broken or unfinished modules, new MemPipeIO converter
2014-09-24 15:11:24 -07:00
Henry Cook
82fe22f958
support for multiple tilelink paramerterizations in same design
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Conflicts:
src/main/scala/cache.scala
2014-09-24 11:30:40 -07:00
Henry Cook
53b8d7b031
use new coherence methods in l2, ready to query dir logic
2014-09-20 18:01:14 -07:00
Henry Cook
149d51d644
more coherence API cleanup
2014-09-20 16:57:13 -07:00
Henry Cook
faed47d131
use thunk for dir info
2014-09-20 16:54:28 -07:00
Henry Cook
f7b1e23ead
functional style on MuxBundle
2014-09-20 16:54:28 -07:00
Yunsup Lee
0b51d70bd2
add LICENSE
2014-09-12 15:31:38 -07:00
Yunsup Lee
f8d450b4e2
mark DRAMSideLLC as HasKnownBug
2014-09-11 22:06:03 -07:00
Henry Cook
712f3a754d
merge in master
2014-09-02 12:34:42 -07:00
Henry Cook
17b2359c9a
htif parameters trait
2014-08-24 19:27:58 -07:00
Henry Cook
dc5643b12f
Final parameter refactor.
2014-08-23 01:19:36 -07:00
Henry Cook
e26f8a6f6a
Fix errors in derived cache params
2014-08-12 14:55:44 -07:00
Henry Cook
9ab3a4262c
Cache utility traits. Completely compiles, asm tests hang.
2014-08-11 18:35:49 -07:00
Henry Cook
f411fdcce3
Full conversion to params. Compiles but does not elaborate.
2014-08-08 12:21:57 -07:00
Henry Cook
3c329df7e7
refactor Metadata, clean and expand coherence API
2014-05-28 13:35:08 -07:00
Andrew Waterman
364a6de214
Use Mem instead of Vec[Reg]
2014-05-18 19:26:35 -07:00
Henry Cook
0e39346a12
L2-specific metadataarray wrapper, hookups to tshrfile
2014-05-07 01:51:46 -07:00
Henry Cook
bc3ef1011e
correct use of function value to initialize MetaDataArray
2014-05-06 12:59:45 -07:00
Henry Cook
45172f1f37
parameterize metadataarray
2014-05-01 01:44:59 -07:00
Henry Cook
0237229921
client/master -> inner/outer
2014-04-29 16:49:18 -07:00
Henry Cook
52c6de5641
DRAMSideLLCLike trait. TSHRFile. New L2 config objects.
2014-04-26 19:11:36 -07:00
Henry Cook
1163131d1e
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:17:05 -07:00
Henry Cook
3f53d532c2
uniquify tilelink conf val name for easier subtyping
2014-04-26 14:58:38 -07:00
Henry Cook
f8f29c69b8
MetaData & friends moved to uncore/
2014-04-23 16:24:20 -07:00
Henry Cook
39681303b8
beginning of l2 cache
2014-04-22 16:58:15 -07:00
Henry Cook
5613dc7d1b
replaced Lists with Vecs
2014-04-18 17:26:56 -07:00
Henry Cook
b1df49ba30
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:35:43 -07:00
Henry Cook
fbca7c6bb3
refactor ioMem and associcated constants. merge Aqcuire and AcquireData
2014-04-10 12:35:43 -07:00
Andrew Waterman
02dbd6b0aa
Don't assign to your own inputs
2014-02-12 18:39:40 -08:00
Henry Cook
bbf8010230
cleanups supporting uncore hierarchy
2014-01-31 15:59:21 -08:00
Andrew Waterman
3e634aef1d
Fix HTIF for cache line sizes other than 64 B
2014-01-22 18:20:36 -08:00
Andrew Waterman
4f1213cb8b
Fix Scala integer overflow
2014-01-13 21:45:14 -08:00
Andrew Waterman
acc0d2b06c
Only use LSBs for HTIF control regs
...
For now, at least...
2013-11-25 04:34:16 -08:00
Yunsup Lee
056bb156ca
make CacheConstants an object
2013-11-20 16:43:55 -08:00
Yunsup Lee
f13d76628b
forgot to put htif into uncore package
2013-11-07 15:42:10 -08:00
Yunsup Lee
c350cbd6ea
move htif to uncore
2013-11-07 13:19:04 -08:00
Yunsup Lee
f440df5338
rename M_FENCE to M_NOP
2013-10-28 22:37:41 -07:00
Huy Vo
cc3dc1bd0f
bug fix
2013-09-19 20:10:56 -07:00
Andrew Waterman
cc7783404d
Add memory command M_XA_XOR
2013-09-12 16:09:53 -07:00
Henry Cook
1cac26fd76
NetworkIOs no longer use thunks
2013-09-10 16:15:41 -07:00
Henry Cook
ee98cd8378
new enum syntax
2013-09-10 10:54:51 -07:00
Stephen Twigg
e23e8e3850
Merge branch 'master' into chisel-v2
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Conflicts:
src/main/scala/memserdes.scala
2013-09-05 16:17:34 -07:00
Henry Cook
b80f45f8f2
Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2
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Conflicts:
src/main/scala/llc.scala
src/main/scala/slowio.scala
2013-08-15 16:22:12 -07:00
Henry Cook
3763cd0004
standardizing sbt build conventions
2013-08-15 15:57:16 -07:00