riscv/rocket-chip
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L2 alloc cleanup

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This commit is contained in:
Henry Cook 2015-05-12 17:14:06 -07:00
parent 5fdae2cb61
commit 172c372d3e
2 changed files with 5 additions and 2 deletions
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4
uncore/src/main/scala/cache.scala
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@ -836,7 +836,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
// We write data to the cache at this level if it was Put here with allocate flag,
// written back dirty, or refilled from outer memory.
pending_writes := (pending_writes & dropPendingBit(io.data.write)) |
addPendingBitWhenBeatHasData(io.inner.acquire) |
addPendingBitWhenBeatHasDataAndAllocs(io.inner.acquire) |
addPendingBitWhenBeatHasData(io.inner.release) |
addPendingBitWhenBeatHasData(io.outer.grant)
val curr_write_beat = PriorityEncoder(pending_writes)
@ -887,7 +887,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
SInt(-1, width = innerDataBeats),
(addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire) |
addPendingBitWhenBeatHasPartialWritemask(io.inner.acquire)).toUInt)
pending_writes := addPendingBitWhenBeatHasData(io.inner.acquire)
pending_writes := addPendingBitWhenBeatHasDataAndAllocs(io.inner.acquire)
pending_resps := UInt(0)
pending_ignt_data := UInt(0)
pending_meta_write := UInt(0)

3
uncore/src/main/scala/uncore.scala
View File

@ -114,6 +114,9 @@ abstract class XactTracker extends CoherenceAgentModule with HasDataBeatCounters
def addPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt =
addPendingBitWhenBeat(in.fire() && in.bits.hasData(), in.bits)
def addPendingBitWhenBeatHasDataAndAllocs(in: DecoupledIO[AcquireFromSrc]): UInt =
addPendingBitWhenBeat(in.fire() && in.bits.hasData() && in.bits.allocate(), in.bits)
def addPendingBitWhenBeatIsGetOrAtomic(in: DecoupledIO[AcquireFromSrc]): UInt = {
val a = in.bits
val isGetOrAtomic = a.isBuiltInType() &&