riscv/rocket-chip
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clean up incoherent and probe flags

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This commit is contained in:
Henry Cook 2015-03-12 16:22:14 -07:00
parent dcc84c4dd3
commit 8181262419
3 changed files with 32 additions and 29 deletions
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30
uncore/src/main/scala/broadcast.scala
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@ -219,16 +219,15 @@ class BroadcastAcquireTracker(trackerId: Int, bankId: Int) extends BroadcastXact
Vec(Acquire.getType, Acquire.putType, Acquire.putAtomicType).contains(xact.a_type)),
"Broadcast Hub does not support PutAtomics or subblock Gets/Puts") // TODO
val release_count = Reg(init=UInt(0, width = log2Up(nClients)))
val probe_flags = Reg(init=Bits(0, width = nClients))
val curr_p_id = PriorityEncoder(probe_flags)
val probe_initial_flags = Bits(width = nClients)
probe_initial_flags := Bits(0)
// issue self-probes for uncached read xacts to facilitate I$ coherence
val release_count = Reg(init=UInt(0, width = log2Up(nCoherentClients+1)))
val pending_probes = Reg(init=Bits(0, width = nCoherentClients))
val curr_p_id = PriorityEncoder(pending_probes)
val full_sharers = coh.full()
val probe_self = io.inner.acquire.bits.payload.requiresSelfProbe()
val myflag = Mux(probe_self, Bits(0),
UIntToOH(io.inner.acquire.bits.header.src(log2Up(nClients)-1,0)))
probe_initial_flags := ~(io.incoherent.toBits | myflag)
val mask_self = Mux(probe_self,
full_sharers | UInt(UInt(1) << xact_src, width = nCoherentClients),
full_sharers & ~UInt(UInt(1) << xact_src, width = nCoherentClients))
val mask_incoherent = mask_self & ~io.incoherent.toBits
val collect_iacq_data = Reg(init=Bool(false))
val iacq_data_valid = Reg(init=Bits(0, width = innerDataBeats))
@ -307,18 +306,21 @@ class BroadcastAcquireTracker(trackerId: Int, bankId: Int) extends BroadcastXact
data_buffer(UInt(0)) := io.iacq().data
collect_iacq_data := io.iacq().hasMultibeatData()
iacq_data_valid := io.iacq().hasData() << io.iacq().addr_beat
probe_flags := probe_initial_flags
release_count := PopCount(probe_initial_flags)
state := Mux(probe_initial_flags.orR, s_probe,
val needs_probes = mask_incoherent.orR
when(needs_probes) {
pending_probes := mask_incoherent
release_count := PopCount(mask_incoherent)
}
state := Mux(needs_probes, s_probe,
Mux(pending_outer_write_, s_mem_write,
Mux(pending_outer_read_, s_mem_read, s_make_grant)))
}
}
is(s_probe) {
// Generate probes
io.inner.probe.valid := probe_flags.orR
io.inner.probe.valid := pending_probes.orR
when(io.inner.probe.ready) {
probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
pending_probes := pending_probes & ~UIntToOH(curr_p_id)
}
// Handle releases, which may have data to be written back

29
uncore/src/main/scala/cache.scala
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@ -596,13 +596,14 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
dst = io.inner.grant.bits.header.dst),
pending_coh.outer)
val release_count = Reg(init = UInt(0, width = log2Up(nClients+1)))
val pending_probes = Reg(init = Bits(0, width = nClients))
val release_count = Reg(init = UInt(0, width = log2Up(nCoherentClients+1)))
val pending_probes = Reg(init = Bits(0, width = nCoherentClients))
val curr_p_id = PriorityEncoder(pending_probes)
val full_sharers = io.meta.resp.bits.meta.coh.inner.full()
val mask_self = Mux(xact.requiresSelfProbe(),
full_sharers | (UInt(1) << xact_src),
full_sharers & ~UInt(UInt(1) << xact_src, width = nClients))
val probe_self = xact.requiresSelfProbe()
val mask_self = Mux(probe_self,
full_sharers | UInt(UInt(1) << xact_src, width = nCoherentClients),
full_sharers & ~UInt(UInt(1) << xact_src, width = nCoherentClients))
val mask_incoherent = mask_self & ~io.incoherent.toBits
val collect_iacq_data = Reg(init=Bool(false))
@ -770,8 +771,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
val _needs_probes = _tag_match && _coh.inner.requiresProbes(xact)
when(_is_hit) { pending_coh := pending_coh_on_hit }
when(_needs_probes) {
pending_probes := mask_incoherent(nCoherentClients-1,0)
release_count := PopCount(mask_incoherent(nCoherentClients-1,0))
pending_probes := mask_incoherent
release_count := PopCount(mask_incoherent)
}
state := Mux(_tag_match,
Mux(_needs_probes, s_probe, Mux(_is_hit, s_data_read, s_outer_acquire)), // Probe, hit or upgrade
@ -920,9 +921,11 @@ class L2WritebackUnit(trackerId: Int, bankId: Int) extends L2XactTracker {
val pending_finish = Reg{ io.outer.finish.bits.clone }
val irel_had_data = Reg(init = Bool(false))
val release_count = Reg(init = UInt(0, width = log2Up(nClients+1)))
val pending_probes = Reg(init = Bits(0, width = nClients))
val release_count = Reg(init = UInt(0, width = log2Up(nCoherentClients+1)))
val pending_probes = Reg(init = Bits(0, width = nCoherentClients))
val curr_p_id = PriorityEncoder(pending_probes)
val full_sharers = io.wb.req.bits.coh.inner.full()
val mask_incoherent = full_sharers & ~io.incoherent.toBits
val irel_data_done = connectIncomingDataBeatCounter(io.inner.release)
val (orel_data_cnt, orel_data_done) = connectOutgoingDataBeatCounter(io.outer.release)
@ -985,12 +988,10 @@ class L2WritebackUnit(trackerId: Int, bankId: Int) extends L2XactTracker {
xact_way_en := io.wb.req.bits.way_en
xact_id := io.wb.req.bits.id
irel_had_data := Bool(false)
val coh = io.wb.req.bits.coh
val needs_probes = coh.inner.requiresProbesOnVoluntaryWriteback()
val needs_probes = io.wb.req.bits.coh.inner.requiresProbesOnVoluntaryWriteback()
when(needs_probes) {
val mask_incoherent = coh.inner.full() & ~io.incoherent.toBits
pending_probes := mask_incoherent(nCoherentClients-1,0)
release_count := PopCount(mask_incoherent(nCoherentClients-1,0))
pending_probes := mask_incoherent
release_count := PopCount(mask_incoherent)
}
state := Mux(needs_probes, s_probe, s_data_read)
}

2
uncore/src/main/scala/uncore.scala
View File

@ -73,7 +73,7 @@ trait HasCoherenceAgentWiringHelpers {
trait HasInnerTLIO extends CoherenceAgentBundle {
val inner = Bundle(new TileLinkIO)(innerTLParams).flip
val incoherent = Vec.fill(nClients){Bool()}.asInput
val incoherent = Vec.fill(nCoherentClients){Bool()}.asInput
def iacq(dummy: Int = 0) = inner.acquire.bits.payload
def iprb(dummy: Int = 0) = inner.probe.bits.payload
def irel(dummy: Int = 0) = inner.release.bits.payload