write back meta data when cache miss even when coherence meta data is clean
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@ -868,9 +868,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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is(s_inner_grant) {
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io.inner.grant.valid := Bool(true)
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when(ignt_data_done) {
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val meta = pending_coh_on_ignt != xact_meta.coh
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when(meta) { pending_coh := pending_coh_on_ignt }
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state := Mux(meta, s_meta_write,
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val coh_dirty = pending_coh_on_ignt != xact_meta.coh
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when(coh_dirty) { pending_coh := pending_coh_on_ignt }
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state := Mux(!is_hit || coh_dirty, s_meta_write,
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Mux(io.ignt().requiresAck(), s_inner_finish, s_idle))
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}
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}
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