first cut at pending scoreboarding
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@ -446,17 +446,28 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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(Mux(!full_block, beat, multi_cnt), Mux(!full_block, inc, multi_done))
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} else { (UInt(0), inc) }
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}
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def connectInternalDataBeatCounter[T <: HasL2BeatAddr](
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in: DecoupledIO[T],
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beat: UInt = UInt(0),
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full_block: Bool = Bool(true)) = {
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connectDataBeatCounter(in.fire(), in.bits, beat, full_block)
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}
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def connectInternalDataBeatCounter[T <: HasL2Data](
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in: ValidIO[T],
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full_block: Bool = Bool(true)) = {
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connectDataBeatCounter(in.valid, in.bits, UInt(0), full_block)._2
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}
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def addInternalPendingBit[T <: HasL2BeatAddr](in: DecoupledIO[T]) =
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Fill(in.bits.refillCycles, in.fire()) & UIntToOH(in.bits.addr_beat)
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def dropPendingBit[T <: HasL2BeatAddr] (in: DecoupledIO[T]) =
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Fill(in.bits.refillCycles, in.fire()) & ~UIntToOH(in.bits.addr_beat)
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def dropInternalPendingBit[T <: HasL2BeatAddr] (in: ValidIO[T]) =
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Fill(in.bits.refillCycles, in.valid) & ~UIntToOH(in.bits.addr_beat)
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}
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class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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@ -591,8 +602,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val xact_meta = Reg{ new L2Metadata }
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val xact_way_en = Reg{ Bits(width = nWays) }
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val pending_coh = Reg{ xact_meta.coh.clone }
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val pending_finish = Reg{ io.outer.finish.bits.clone }
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val ignt_q = Module(new Queue(new L2SecondaryMissInfo, nSecondaryMisses))(innerTLParams)
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val is_hit = xact_tag_match && xact_meta.coh.outer.isHit(xact.op_code())
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val do_allocate = xact.allocate()
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@ -611,18 +620,38 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val mask_incoherent = mask_self & ~io.incoherent.toBits
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val irel_data_done = connectIncomingDataBeatCounter(io.inner.release)
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val ognt_data_done = connectIncomingDataBeatCounter(io.outer.grant)
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val (oacq_data_cnt, oacq_data_done) = connectOutgoingDataBeatCounter(io.outer.acquire, xact.addr_beat)
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val ognt_data_done = connectIncomingDataBeatCounter(io.outer.grant)
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val pending_ofin = Reg{ io.outer.finish.bits.clone }
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val ignt_q = Module(new Queue(new L2SecondaryMissInfo, nSecondaryMisses))(innerTLParams)
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val (ignt_data_idx, ignt_data_done) = connectOutgoingDataBeatCounter(io.inner.grant, ignt_q.io.deq.bits.addr_beat)
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ignt_q.io.enq.valid := Bool(false)
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ignt_q.io.enq.bits.client_xact_id := io.iacq().client_xact_id
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ignt_q.io.enq.bits.addr_beat := io.iacq().addr_beat
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ignt_q.io.deq.ready := ignt_data_done
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val ifin_cnt = Reg(init = UInt(0, width = log2Up(nSecondaryMisses+1)))
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when(ignt_data_done) { ifin_cnt := ifin_cnt + UInt(1) }
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val pending_reads = Reg(init=Bits(0, width = innerDataBeats))
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val pending_writes = Reg(init=Bits(0, width = innerDataBeats))
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val pending_resps = Reg(init=Bits(0, width = innerDataBeats))
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pending_reads := pending_reads |
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addPendingBit(io.inner.acquire) |
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dropPendingBit(io.data.read)
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val curr_read_beat = PriorityEncoder(pending_reads)
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val pending_writes = Reg(init=Bits(0, width = innerDataBeats))
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pending_writes := pending_writes |
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addPendingBit(io.inner.acquire) |
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addPendingBit(io.inner.release) |
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addPendingBit(io.outer.grant) &
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dropPendingBit(io.data.write)
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val curr_write_beat = PriorityEncoder(pending_writes)
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val pending_resps = Reg(init=Bits(0, width = innerDataBeats))
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pending_resps := pending_resps |
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addInternalPendingBit(io.data.read) &
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dropInternalPendingBit(io.data.resp)
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val pending_coh_on_hit = HierarchicalMetadata(
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io.meta.resp.bits.meta.coh.inner,
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io.meta.resp.bits.meta.coh.outer.onHit(xact.op_code()))
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@ -720,8 +749,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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io.outer.release.valid := Bool(false)
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io.outer.grant.ready := Bool(false)
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io.outer.finish.valid := Bool(false)
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io.outer.finish.bits := pending_finish
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val pending_finish_on_ognt = io.ognt().makeFinish()
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io.outer.finish.bits := pending_ofin
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val pending_ofin_on_ognt = io.ognt().makeFinish()
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io.inner.probe.valid := Bool(false)
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io.inner.probe.bits.header.src := UInt(bankId)
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@ -739,7 +768,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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amo_result,
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data_buffer(ignt_data_idx)))
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io.ignt().client_xact_id := ignt_q.io.deq.bits.client_xact_id
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ignt_q.io.deq.ready := ignt_data_done
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io.inner.acquire.ready := state === s_idle ||
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can_merge_iacq_put ||
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@ -789,6 +817,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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pending_writes := UInt(0)
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pending_resps := UInt(0)
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ifin_cnt := UInt(0)
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ignt_q.io.enq.valid := Bool(true)
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state := s_meta_read
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}
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}
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@ -842,7 +871,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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when(io.irel().hasData()) {
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pending_coh.outer := pending_ocoh_on_irel
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mergeDataInner(io.irel().addr_beat, io.irel().data)
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pending_writes := pending_writes | UIntToOH(io.irel().addr_beat)
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}
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// We don't decrement release_count until we've received all the data beats.
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when(!io.irel().hasMultibeatData() || irel_data_done) {
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@ -866,14 +894,13 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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when(io.outer.grant.valid) {
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when(io.ognt().hasData()) {
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mergeDataOuter(io.ognt().addr_beat, io.ognt().data)
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pending_writes := pending_writes | UIntToOH(io.ognt().addr_beat)
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}
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when(ognt_data_done) {
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pending_coh := pending_coh_on_ognt
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when(io.ognt().requiresAck()) {
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pending_finish.payload := pending_finish_on_ognt
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pending_finish.header.dst := io.outer.grant.bits.header.src
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pending_finish.header.src := UInt(bankId)
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pending_ofin.payload := pending_ofin_on_ognt
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pending_ofin.header.dst := io.outer.grant.bits.header.src
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pending_ofin.header.src := UInt(bankId)
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state := s_outer_finish
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}.otherwise {
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state := Mux(!do_allocate, s_inner_grant,
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@ -892,18 +919,10 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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is(s_data_read) {
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io.data.read.valid := pending_reads.orR
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when(io.data.read.ready) {
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pending_resps := pending_resps | UIntToOH(curr_read_beat)
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pending_reads := pending_reads & ~UIntToOH(curr_read_beat)
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when(PopCount(pending_reads) <= UInt(1)) { state := s_data_resp }
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}
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when(io.data.resp.valid) {
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mergeDataInternal(io.data.resp.bits.addr_beat, io.data.resp.bits.data)
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pending_resps := pending_resps & ~UIntToOH(io.data.resp.bits.addr_beat)
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}
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when(io.data.read.ready && io.data.resp.valid) {
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pending_resps := (pending_resps &
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~UIntToOH(io.data.resp.bits.addr_beat)) |
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UIntToOH(curr_read_beat)
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}
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}
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is(s_data_resp) {
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@ -918,7 +937,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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is(s_data_write) {
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io.data.write.valid := pending_writes.orR //TODO make sure all acquire data is present
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when(io.data.write.ready) {
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pending_writes := pending_writes & ~UIntToOH(curr_write_beat)
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when(PopCount(pending_writes) <= UInt(1)) { state := s_inner_grant }
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}
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}
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@ -950,20 +968,12 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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}
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}
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ignt_q.io.enq.valid := io.inner.acquire.fire() &&
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(state === s_idle || !xact.hasMultibeatData())
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ignt_q.io.enq.bits.client_xact_id := io.iacq().client_xact_id
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ignt_q.io.enq.bits.addr_beat := io.iacq().addr_beat
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// Handle Get and Put merging
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when(io.inner.acquire.fire()) {
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val beat = io.iacq().addr_beat
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when(io.iacq().hasData()) {
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mergeDataPut(beat, io.iacq().wmask(), io.iacq().data)
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//iacq_data_valid(beat) := Bool(true)
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pending_writes := pending_writes | UIntToOH(io.iacq().addr_beat)
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}
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when(state != s_idle) { pending_reads := pending_reads | UIntToOH(io.iacq().addr_beat) }
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when(io.inner.acquire.fire() && io.iacq().hasData()) {
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mergeDataPut(io.iacq().addr_beat, io.iacq().wmask(), io.iacq().data)
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when(!xact.hasMultibeatData()) { ignt_q.io.enq.valid := Bool(true) }
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//iacq_data_valid(beat) := Bool(true)
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}
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assert(!(state != s_idle && io.inner.acquire.fire() &&
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@ -1007,7 +1017,7 @@ class L2WritebackUnit(trackerId: Int, bankId: Int) extends L2XactTracker {
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val xact_way_en = Reg{ Bits(width = nWays) }
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val data_buffer = Vec.fill(innerDataBeats){ Reg(io.irel().data.clone) }
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val xact_id = Reg{ UInt() }
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val pending_finish = Reg{ io.outer.finish.bits.clone }
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val pending_ofin = Reg{ io.outer.finish.bits.clone }
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val irel_had_data = Reg(init = Bool(false))
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val release_count = Reg(init = UInt(0, width = log2Up(nCoherentClients+1)))
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@ -1043,8 +1053,8 @@ class L2WritebackUnit(trackerId: Int, bankId: Int) extends L2XactTracker {
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io.outer.release.bits.header.src := UInt(bankId)
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io.outer.grant.ready := Bool(false) // default
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io.outer.finish.valid := Bool(false) // default
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io.outer.finish.bits := pending_finish
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val pending_finish_on_ognt = io.ognt().makeFinish()
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io.outer.finish.bits := pending_ofin
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val pending_ofin_on_ognt = io.ognt().makeFinish()
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io.inner.probe.valid := Bool(false)
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io.inner.probe.bits.header.src := UInt(bankId)
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@ -1133,8 +1143,8 @@ class L2WritebackUnit(trackerId: Int, bankId: Int) extends L2XactTracker {
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io.outer.grant.ready := Bool(true)
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when(io.outer.grant.valid) {
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when(io.ognt().requiresAck()) {
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pending_finish.payload := pending_finish_on_ognt
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pending_finish.header.dst := io.outer.grant.bits.header.src
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pending_ofin.payload := pending_ofin_on_ognt
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pending_ofin.header.dst := io.outer.grant.bits.header.src
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state := s_outer_finish
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}.otherwise {
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state := s_wb_resp
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@ -139,12 +139,19 @@ abstract class XactTracker extends CoherenceAgentModule {
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val done = Mux(multi, multi_done, inc)
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(cnt, done)
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}
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def connectOutgoingDataBeatCounter[T <: HasTileLinkData : ClassTag](
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in: DecoupledIO[LogicalNetworkIO[T]],
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beat: UInt = UInt(0)) = {
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connectDataBeatCounter(in.fire(), in.bits.payload, beat)
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}
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def connectIncomingDataBeatCounter[T <: HasTileLinkData : ClassTag](in: DecoupledIO[LogicalNetworkIO[T]]) = {
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connectDataBeatCounter(in.fire(), in.bits.payload, UInt(0))._2
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}
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def addPendingBit[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[LogicalNetworkIO[T]]) = {
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(Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.hasData()) &
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UIntToOH(in.bits.payload.addr_beat))
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}
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}
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