Chisel3 compatibility fixes

uncore/src/main/scala/broadcast.scala

@@ -111,7 +111,7 @@ class L2BroadcastHub extends ManagerCoherenceAgent
   io.outer.acquire.bits.data := MuxLookup(outer_data_ptr.loc, io.irel().data, Array(
                                           inStoreQueue -> sdq(outer_data_ptr.idx),
                                           inVolWBQueue -> vwbdq(outer_data_ptr.idx)))
-  io.outer.acquire.bits.union := Cat(Fill(outer_arb.io.out.acquire.bits.union(1), io.outer.acquire.bits.tlWriteMaskBits),
+  io.outer.acquire.bits.union := Cat(Fill(io.outer.acquire.bits.tlWriteMaskBits, outer_arb.io.out.acquire.bits.union(1)),
                                    outer_arb.io.out.acquire.bits.union(0))
   io.outer <> outer_arb.io.out
 
@@ -221,11 +221,7 @@ class BroadcastAcquireTracker(trackerId: Int) extends BroadcastXactTracker {
   val release_count = Reg(init=UInt(0, width = log2Up(io.inner.tlNCachingClients+1)))
   val pending_probes = Reg(init=Bits(0, width = io.inner.tlNCachingClients))
   val curr_p_id = PriorityEncoder(pending_probes)
-  val full_sharers = coh.full()
-  val probe_self = io.inner.acquire.bits.requiresSelfProbe()
-  val mask_self_true = UInt(UInt(1) << io.inner.acquire.bits.client_id, width = io.inner.tlNCachingClients)
-  val mask_self_false = ~UInt(UInt(1) << io.inner.acquire.bits.client_id, width = io.inner.tlNCachingClients)
-  val mask_self = Mux(probe_self, full_sharers | mask_self_true, full_sharers & mask_self_false)
+  val mask_self = coh.full().bitSet(io.inner.acquire.bits.client_id, io.inner.acquire.bits.requiresSelfProbe())
   val mask_incoherent = mask_self & ~io.incoherent.toBits
 
   val collect_iacq_data = Reg(init=Bool(false))

uncore/src/main/scala/htif.scala

@@ -3,7 +3,7 @@
 package uncore
 
 import Chisel._
-import Node._
+import Chisel.ImplicitConversions._
 import uncore._
 
 case object HTIFWidth extends Field[Int]

uncore/src/main/scala/network.scala

@@ -61,7 +61,7 @@ object DecoupledLogicalNetworkIOWrapper {
       in: DecoupledIO[T],
       src: UInt = UInt(0),
       dst: UInt = UInt(0)): DecoupledIO[LogicalNetworkIO[T]] = {
-    val out = Decoupled(new LogicalNetworkIO(in.bits)).asDirectionless
+    val out = Wire(Decoupled(new LogicalNetworkIO(in.bits)))
     out.valid := in.valid
     out.bits.payload := in.bits
     out.bits.header.dst := dst
@@ -83,7 +83,7 @@ object DecoupledLogicalNetworkIOUnwrapper {
 
 object DefaultFromPhysicalShim {
   def apply[T <: Data](in: DecoupledIO[PhysicalNetworkIO[T]]): DecoupledIO[LogicalNetworkIO[T]] = {
-    val out = Decoupled(new LogicalNetworkIO(in.bits.payload)).asDirectionless
+    val out = Wire(Decoupled(new LogicalNetworkIO(in.bits.payload)))
     out.bits.header := in.bits.header
     out.bits.payload := in.bits.payload
     out.valid := in.valid
@@ -94,7 +94,7 @@ object DefaultFromPhysicalShim {
 
 object DefaultToPhysicalShim {
   def apply[T <: Data](n: Int, in: DecoupledIO[LogicalNetworkIO[T]]): DecoupledIO[PhysicalNetworkIO[T]] = {
-    val out = Decoupled(new PhysicalNetworkIO(n, in.bits.payload)).asDirectionless
+    val out = Wire(Decoupled(new PhysicalNetworkIO(n, in.bits.payload)))
     out.bits.header := in.bits.header
     out.bits.payload := in.bits.payload
     out.valid := in.valid