Merge branch 'master' into gh-pages
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commit
90ced93eeb
@ -60,14 +60,14 @@ class MemPipeIO extends Bundle {
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val resp = Valid(new MemResp).flip
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}
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class MemSerializedIO(w: Int) extends Bundle
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{
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class MemSerializedIO(w: Int) extends Bundle {
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val req = Decoupled(Bits(width = w))
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val resp = Valid(Bits(width = w)).flip
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}
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class MemSerdes(w: Int) extends MIFModule
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class MemSerdes extends MIFModule
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{
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val w = params(HTIFWidth)
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val io = new Bundle {
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val wide = new MemIO().flip
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val narrow = new MemSerializedIO(w)
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@ -517,6 +517,65 @@ object HellaQueue
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}
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}
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class MemIOArbiter(val arbN: Int) extends MIFModule {
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val io = new Bundle {
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val inner = Vec.fill(arbN){new MemIO}.flip
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val outer = new MemIO
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}
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if(arbN > 1) {
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val cmd_arb = Module(new RRArbiter(new MemReqCmd, arbN))
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val choice_q = Module(new Queue(cmd_arb.io.chosen.clone, 4))
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val (data_cnt, data_done) = Counter(io.outer.req_data.fire(), mifDataBeats)
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io.inner.map(_.req_cmd).zipWithIndex.zip(cmd_arb.io.in).map{ case ((req, id), arb) => {
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arb.valid := req.valid
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arb.bits := req.bits
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arb.bits.tag := Cat(req.bits.tag, UInt(id))
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req.ready := arb.ready
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}}
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io.outer.req_cmd.bits := cmd_arb.io.out.bits
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io.outer.req_cmd.valid := cmd_arb.io.out.valid && choice_q.io.enq.ready
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cmd_arb.io.out.ready := io.outer.req_cmd.ready && choice_q.io.enq.ready
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choice_q.io.enq.bits := cmd_arb.io.chosen
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choice_q.io.enq.valid := cmd_arb.io.out.fire() && cmd_arb.io.out.bits.rw
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io.outer.req_data.bits := io.inner(choice_q.io.deq.bits).req_data.bits
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io.outer.req_data.valid := io.inner(choice_q.io.deq.bits).req_data.valid && choice_q.io.deq.valid
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io.inner.map(_.req_data.ready).zipWithIndex.foreach {
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case(r, i) => r := UInt(i) === choice_q.io.deq.bits && choice_q.io.deq.valid
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}
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choice_q.io.deq.ready := data_done
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io.outer.resp.ready := Bool(false)
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for (i <- 0 until arbN) {
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io.inner(i).resp.valid := Bool(false)
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when(io.outer.resp.bits.tag(log2Up(arbN)-1,0).toUInt === UInt(i)) {
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io.inner(i).resp.valid := io.outer.resp.valid
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io.outer.resp.ready := io.inner(i).resp.ready
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}
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io.inner(i).resp.bits := io.outer.resp.bits
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io.inner(i).resp.bits.tag := io.outer.resp.bits.tag >> UInt(log2Up(arbN))
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}
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} else { io.inner.head <> io.outer }
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}
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object MemIOMemPipeIOConverter {
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def apply(in: MemPipeIO): MemIO = {
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val out = new MemIO().asDirectionless
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in.resp.valid := out.resp.valid
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in.resp.bits := out.resp.bits
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out.resp.ready := Bool(true)
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out.req_cmd.valid := in.req_cmd.valid
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out.req_cmd.bits := in.req_cmd.bits
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in.req_cmd.ready := out.req_cmd.ready
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out.req_data.valid := in.req_data.valid
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out.req_data.bits := in.req_data.bits
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in.req_data.ready := out.req_data.ready
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out
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}
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}
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class MemPipeIOMemIOConverter(numRequests: Int) extends MIFModule {
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val io = new Bundle {
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val cpu = new MemIO().flip
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@ -488,7 +488,7 @@ class ProbeToDst extends Probe with HasClientId
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/** Contains factories for [[uncore.Probe]] and [[uncore.ProbeToDst]]
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*
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* In general you should avoid using these factories directly and use
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* [[uncore.ManagerMetadata.makeProbe(UInt,Acquire)*]] instead.
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* [[uncore.ManagerMetadata.makeProbe(UInt,Acquire)* makeProbe]] instead.
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*
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* @param dst id of client to which probe should be sent
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* @param p_type custom probe type
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