cleanup pending signals
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parent
002851f836
commit
004ad11af6
@ -606,9 +606,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val xact_meta = Reg{ new L2Metadata }
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val xact_way_en = Reg{ Bits(width = nWays) }
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val pending_coh = Reg{ xact_meta.coh.clone }
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val present_puts = Reg(init=Bits(0, width = innerDataBeats))
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present_puts := (present_puts | addPendingBitWhenHasData(io.inner.acquire))
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val needs_more_put_data = !present_puts.andR
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val pending_puts = Reg(init=Bits(0, width = innerDataBeats))
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pending_puts := (pending_puts & dropPendingBitWhenHasData(io.inner.acquire))
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val needs_more_put_data = pending_puts.orR
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val do_allocate = xact.allocate()
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val release_count = Reg(init = UInt(0, width = log2Up(nCoherentClients+1)))
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@ -648,9 +648,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val pending_reads = Reg(init=Bits(0, width = innerDataBeats))
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pending_reads := (pending_reads |
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addPendingBitWhenWmaskIsNotFull(io.inner.acquire)) &
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addPendingBitWhenGetOrAtomic(io.inner.acquire)) &
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(dropPendingBit(io.data.read) &
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dropPendingBitWhenWmaskIsFull(io.inner.acquire) &
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dropPendingBitWhenHasData(io.inner.release) &
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dropPendingBitWhenHasData(io.outer.grant))
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val curr_read_beat = PriorityEncoder(pending_reads)
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@ -824,14 +823,12 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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xact := io.iacq()
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xact.data := UInt(0)
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wmask_buffer.foreach { w => w := UInt(0) }
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present_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
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addPendingBitWhenHasData(io.inner.acquire),
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SInt(-1, width = innerDataBeats)).toUInt
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pending_reads := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
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UInt(0),
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Mux(io.iacq().isSubBlockType(),
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addPendingBitWhenWmaskIsNotFull(io.inner.acquire),
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SInt(-1, width = innerDataBeats)).toUInt)
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pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
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dropPendingBitWhenHasData(io.inner.acquire),
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UInt(0))
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pending_reads := Mux(io.iacq().isBuiltInType(),
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addPendingBitWhenGetOrAtomic(io.inner.acquire),
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SInt(-1, width = innerDataBeats)).toUInt
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pending_writes := addPendingBitWhenHasData(io.inner.acquire)
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pending_resps := UInt(0)
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pending_ignt_data := UInt(0)
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@ -160,14 +160,10 @@ abstract class XactTracker extends CoherenceAgentModule {
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~UIntToOH(in.bits.payload.addr_beat)
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}
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//TODO | with existing wmask_buffer?
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def addPendingBitWhenWmaskIsNotFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
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Fill(in.bits.payload.tlDataBeats, in.fire() && !in.bits.payload.wmask().andR) &
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UIntToOH(in.bits.payload.addr_beat)
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}
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def dropPendingBitWhenWmaskIsFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
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~Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.wmask().andR) |
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~UIntToOH(in.bits.payload.addr_beat)
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def addPendingBitWhenGetOrAtomic(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
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val a = in.bits.payload
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Fill(a.tlDataBeats, in.fire() && a.isBuiltInType() &&
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(a.is(Acquire.getType) || a.is(Acquire.getBlockType) || a.is(Acquire.putAtomicType))) &
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UIntToOH(a.addr_beat)
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}
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}
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