riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Remove master_xact_id from Probe and Release

Browse Source
This commit is contained in:
Henry Cook 2014-11-05 14:21:38 -08:00
parent d735f64110
commit 10309849b7
2 changed files with 15 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
uncore/src/main/scala/tilelink.scala
View File

@ -79,52 +79,41 @@ class Acquire extends ClientSourcedMessage
val atomic_opcode = Bits(width = params(TLAtomicOpBits))
}
object Probe
{
def apply(p_type: UInt, addr: UInt, master_xact_id: UInt) = {
object Probe {
def apply(p_type: UInt, addr: UInt) = {
val prb = new Probe
prb.p_type := p_type
prb.addr := addr
prb.master_xact_id := master_xact_id
prb
}
}
class Probe extends MasterSourcedMessage
with HasPhysicalAddress
with HasMasterTransactionId {
with HasPhysicalAddress {
val p_type = UInt(width = params(TLCoherence).probeTypeWidth)
}
object Release
{
def apply(r_type: UInt, addr: UInt, data: UInt): Release = {
val rel = new Release
rel.r_type := r_type
rel.addr := addr
rel.data := data
rel
}
def apply(r_type: UInt, addr: UInt, client_xact_id: UInt, master_xact_id: UInt): Release = {
object Release {
def apply(r_type: UInt, addr: UInt, client_xact_id: UInt, data: UInt): Release = {
val rel = new Release
rel.r_type := r_type
rel.addr := addr
rel.client_xact_id := client_xact_id
rel.master_xact_id := master_xact_id
rel.data := UInt(0)
rel
}
def apply(r_type: UInt, addr: UInt, client_xact_id: UInt, master_xact_id: UInt, data: UInt): Release = {
val rel = apply(r_type, addr, client_xact_id, master_xact_id)
rel.data := data
rel
}
def apply(r_type: UInt, addr: UInt, client_xact_id: UInt): Release = {
apply(r_type, addr, client_xact_id, UInt(0))
}
def apply(r_type: UInt, addr: UInt): Release = {
apply(r_type, addr, UInt(0), UInt(0))
}
}
class Release extends ClientSourcedMessage
with HasPhysicalAddress
with HasClientTransactionId
with HasMasterTransactionId
with HasTileLinkData {
val r_type = UInt(width = params(TLCoherence).releaseTypeWidth)
}

8
uncore/src/main/scala/uncore.scala
View File

@ -62,8 +62,8 @@ class L2CoherenceAgent(bankId: Int, innerId: String, outerId: String) extends
val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
val block_releases = Bool(false)
val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
val release_idx = Mux(voluntary, UInt(0), release.bits.payload.master_xact_id)
val release_idx = Mux(voluntary, UInt(0), conflict_idx)
// TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
for( i <- 0 until trackerList.size ) {
val t = trackerList(i).io.inner
t.release.bits := release.bits
@ -200,9 +200,7 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
io.inner.probe.valid := Bool(false)
io.inner.probe.bits.header.src := UInt(bankId)
io.inner.probe.bits.header.dst := curr_p_id
io.inner.probe.bits.payload := Probe(co.getProbeType(xact, co.masterMetadataOnFlush),
xact.addr,
UInt(trackerId))
io.inner.probe.bits.payload := Probe(co.getProbeType(xact, co.masterMetadataOnFlush), xact.addr)
val grant_type = co.getGrantType(xact, co.masterMetadataOnFlush)
io.inner.grant.valid := Bool(false)