fix up and simplify TL -> NASTI converter logic
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d391f97953
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@ -1418,20 +1418,16 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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io.nasti.w.valid := Bool(false)
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val dst_off = dstIdBits + tlClientXactIdBits
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val acq_has_data = io.tl.acquire.bits.hasData()
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val is_write = io.tl.acquire.valid && acq_has_data
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val has_data = io.tl.acquire.bits.hasData()
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val is_write = io.tl.acquire.valid && has_data
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// Decompose outgoing TL Acquires into Nasti address and data channels
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val active_out = Reg(init=Bool(false))
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val cmd_sent_out = Reg(init=Bool(false))
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val tag_out = Reg(UInt(width = nastiXIdBits))
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val addr_out = Reg(UInt(width = nastiXAddrBits))
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val has_data = Reg(init=Bool(false))
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val is_subblock = io.tl.acquire.bits.isSubBlockType()
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val is_multibeat = io.tl.acquire.bits.hasMultibeatData()
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val (tl_cnt_out, tl_wrap_out) = Counter(
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io.tl.acquire.fire() && io.tl.acquire.bits.hasMultibeatData(), tlDataBeats)
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val tl_done_out = Reg(init=Bool(false))
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io.tl.acquire.fire() && is_multibeat, tlDataBeats)
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// Reorder queue saves extra information needed to send correct
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// grant back to TL client
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val roq = Module(new ReorderQueue(
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new NastiIOTileLinkIOConverterInfo,
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nastiRIdBits, tlMaxClientsPerPort))
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@ -1439,68 +1435,60 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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val (nasti_cnt_out, nasti_wrap_out) = Counter(
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io.nasti.r.fire() && !roq.io.deq.data.subblock, tlDataBeats)
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roq.io.enq.valid := io.tl.acquire.fire() && !acq_has_data
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roq.io.enq.valid := io.tl.acquire.fire() && !has_data
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roq.io.enq.bits.tag := io.nasti.ar.bits.id
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roq.io.enq.bits.data.byteOff := io.tl.acquire.bits.addr_byte()
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roq.io.enq.bits.data.subblock := is_subblock
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roq.io.deq.valid := io.nasti.r.fire() && (nasti_wrap_out || roq.io.deq.data.subblock)
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roq.io.deq.tag := io.nasti.r.bits.id
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// Decompose outgoing TL Acquires into Nasti address and data channels
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = tag_out,
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addr = addr_out,
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id = io.tl.acquire.bits.client_xact_id,
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addr = io.tl.acquire.bits.full_addr(),
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size = Mux(is_subblock,
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opSizeToXSize(io.tl.acquire.bits.op_size()),
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UInt(log2Ceil(tlDataBytes))),
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len = Mux(is_subblock, UInt(0), UInt(tlDataBeats - 1)))
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = io.tl.acquire.bits.client_xact_id,
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addr = io.tl.acquire.bits.full_addr(),
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size = UInt(log2Ceil(tlDataBytes)),
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len = Mux(has_data, UInt(tlDataBeats - 1), UInt(0)))
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io.nasti.aw.bits := io.nasti.ar.bits
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len = Mux(is_multibeat, UInt(tlDataBeats - 1), UInt(0)))
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io.nasti.w.bits := NastiWriteDataChannel(
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data = io.tl.acquire.bits.data,
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strb = io.tl.acquire.bits.wmask(),
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last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock))
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when(!active_out){
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io.tl.acquire.ready := io.nasti.w.ready
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io.nasti.w.valid := is_write
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when(io.tl.acquire.fire()) {
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active_out := (!is_write && !io.nasti.ar.ready) ||
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(is_write && !(io.nasti.aw.ready && io.nasti.w.ready)) ||
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(io.nasti.w.valid && Bool(tlDataBeats > 1))
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io.nasti.aw.valid := is_write
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io.nasti.ar.valid := !is_write
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cmd_sent_out := (!is_write && io.nasti.ar.ready) || (is_write && io.nasti.aw.ready)
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val tag = io.tl.acquire.bits.client_xact_id
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val addr = io.tl.acquire.bits.full_addr()
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when(is_write) {
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io.nasti.aw.bits.id := tag
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io.nasti.aw.bits.addr := addr
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io.nasti.aw.bits.len := Mux(!is_subblock, UInt(tlDataBeats-1), UInt(0))
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} .otherwise {
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io.nasti.ar.bits.id := tag
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io.nasti.ar.bits.addr := addr
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io.nasti.ar.bits.len := Mux(!is_subblock, UInt(tlDataBeats-1), UInt(0))
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io.nasti.ar.bits.size := opSizeToXSize(io.tl.acquire.bits.op_size())
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}
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tag_out := tag
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addr_out := addr
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has_data := acq_has_data
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tl_done_out := tl_wrap_out || is_subblock
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}
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}
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when(active_out) {
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io.nasti.ar.valid := !cmd_sent_out && !has_data
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io.nasti.aw.valid := !cmd_sent_out && has_data
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cmd_sent_out := cmd_sent_out || io.nasti.ar.fire() || io.nasti.aw.fire()
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when(has_data && !tl_done_out) {
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io.tl.acquire.ready := io.nasti.w.ready
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io.nasti.w.valid := io.tl.acquire.valid
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}
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when(tl_wrap_out) { tl_done_out := Bool(true) }
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when(cmd_sent_out && roq.io.enq.ready && (!has_data || tl_done_out)) {
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active_out := Bool(false)
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val w_inflight = Reg(init = Bool(false))
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when (!w_inflight && io.tl.acquire.valid) {
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when (has_data) {
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// For Put/PutBlock, make sure aw and w channel are both ready before
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// we send the first beat
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io.tl.acquire.ready := io.nasti.aw.ready && io.nasti.w.ready
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io.nasti.aw.valid := io.nasti.w.ready
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io.nasti.w.valid := io.nasti.aw.ready
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// For Putblock, use a different state for the subsequent beats
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when (io.tl.acquire.ready && is_multibeat) { w_inflight := Bool(true) }
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} .otherwise {
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// For Get/GetBlock, make sure Reorder queue can accept new entry
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io.tl.acquire.ready := io.nasti.ar.ready && roq.io.enq.ready
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io.nasti.ar.valid := roq.io.enq.ready
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}
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}
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when (w_inflight) {
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io.nasti.w.valid := io.tl.acquire.valid
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io.tl.acquire.ready := io.nasti.w.ready
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when (tl_wrap_out) { w_inflight := Bool(false) }
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}
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// Aggregate incoming NASTI responses into TL Grants
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val (tl_cnt_in, tl_wrap_in) = Counter(io.tl.grant.fire() && io.tl.grant.bits.hasMultibeatData(), tlDataBeats)
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val (tl_cnt_in, tl_wrap_in) = Counter(
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io.tl.grant.fire() && io.tl.grant.bits.hasMultibeatData(), tlDataBeats)
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val gnt_arb = Module(new Arbiter(new GrantToDst, 2))
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io.tl.grant <> gnt_arb.io.out
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