move htif to uncore
This commit is contained in:
Yunsup Lee
parent
f440df5338
commit
c350cbd6ea
267
uncore/src/main/scala/htif.scala
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267
uncore/src/main/scala/htif.scala
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package rocket
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import Chisel._
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import Node._
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import uncore._
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class HostIO(val w: Int) extends Bundle
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{
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val clk = Bool(OUTPUT)
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val clk_edge = Bool(OUTPUT)
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val in = Decoupled(Bits(width = w)).flip
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val out = Decoupled(Bits(width = w))
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val debug_stats_pcr = Bool(OUTPUT)
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}
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class PCRReq extends Bundle
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{
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val rw = Bool()
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val addr = Bits(width = 5)
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val data = Bits(width = 64)
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}
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class HTIFIO(ntiles: Int) extends Bundle
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{
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val reset = Bool(INPUT)
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val id = UInt(INPUT, log2Up(ntiles))
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val pcr_req = Decoupled(new PCRReq).flip
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val pcr_rep = Decoupled(Bits(width = 64))
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val ipi_req = Decoupled(Bits(width = log2Up(ntiles)))
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val ipi_rep = Decoupled(Bool()).flip
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val debug_stats_pcr = Bool(OUTPUT)
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// wired directly to stats register
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// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
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}
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class SCRIO(n: Int) extends Bundle
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{
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val rdata = Vec.fill(n){Bits(INPUT, 64)}
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val wen = Bool(OUTPUT)
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val waddr = UInt(OUTPUT, log2Up(n))
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val wdata = Bits(OUTPUT, 64)
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}
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class HTIF(w: Int, pcr_RESET: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extends Module with ClientCoherenceAgent
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{
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implicit val (ln, co) = (conf.ln, conf.co)
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val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client
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val io = new Bundle {
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val host = new HostIO(w)
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val cpu = Vec.fill(nTiles){new HTIFIO(nTiles).flip}
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val mem = new TileLinkIO
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val scr = new SCRIO(nSCR)
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}
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io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_)
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// system is 'interesting' if any tile is 'interesting'
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val short_request_bits = 64
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val long_request_bits = 576
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require(short_request_bits % w == 0)
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val rx_count_w = 13 + log2Up(64) - log2Up(w) // data size field is 12 bits
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val rx_count = Reg(init=UInt(0,rx_count_w))
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val rx_shifter = Reg(Bits(width = short_request_bits))
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val rx_shifter_in = Cat(io.host.in.bits, rx_shifter(short_request_bits-1,w))
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val next_cmd = rx_shifter_in(3,0)
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val cmd = Reg(Bits())
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val size = Reg(Bits())
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val pos = Reg(Bits())
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val seqno = Reg(Bits())
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val addr = Reg(Bits())
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when (io.host.in.valid && io.host.in.ready) {
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rx_shifter := rx_shifter_in
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rx_count := rx_count + UInt(1)
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when (rx_count === UInt(short_request_bits/w-1)) {
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cmd := next_cmd
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size := rx_shifter_in(15,4)
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pos := rx_shifter_in(15,4+OFFSET_BITS-3)
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seqno := rx_shifter_in(23,16)
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addr := rx_shifter_in(63,24)
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}
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}
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val rx_word_count = (rx_count >> UInt(log2Up(short_request_bits/w)))
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val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
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val packet_ram_depth = long_request_bits/short_request_bits-1
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val packet_ram = Vec.fill(packet_ram_depth){Reg(Bits(width = short_request_bits))}
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when (rx_word_done && io.host.in.ready) {
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packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in
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}
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(UInt(), 6)
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val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
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val pcr_coreid = addr(log2Up(nTiles)-1+20+1,20)
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val pcr_wdata = packet_ram(0)
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val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
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val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, bad_mem_packet,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, size != UInt(1),
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Bool(true)))
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val tx_count = Reg(init=UInt(0, rx_count_w))
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val tx_subword_count = tx_count(log2Up(short_request_bits/w)-1,0)
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val tx_word_count = tx_count(rx_count_w-1, log2Up(short_request_bits/w))
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val packet_ram_raddr = tx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)
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when (io.host.out.valid && io.host.out.ready) {
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tx_count := tx_count + UInt(1)
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}
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val rx_done = rx_word_done && Mux(rx_word_count === UInt(0), next_cmd != cmd_writemem && next_cmd != cmd_writecr, rx_word_count === size || rx_word_count(log2Up(packet_ram_depth)-1,0) === UInt(0))
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val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr || cmd === cmd_writecr), size, UInt(0))
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val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UInt(0) && packet_ram_raddr.andR)
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val mem_acked = Reg(init=Bool(false))
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val mem_gxid = Reg(Bits())
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val mem_gsrc = Reg(UInt(width = conf.ln.idBits))
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val mem_needs_ack = Reg(Bool())
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when (io.mem.grant.valid) {
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mem_acked := Bool(true)
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mem_gxid := io.mem.grant.bits.payload.master_xact_id
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mem_gsrc := io.mem.grant.bits.header.src
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mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload)
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}
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io.mem.grant.ready := Bool(true)
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val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(UInt(), 9)
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val state = Reg(init=state_rx)
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val rx_cmd = Mux(rx_word_count === UInt(0), next_cmd, cmd)
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when (state === state_rx && rx_done) {
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state := Mux(rx_cmd === cmd_readmem || rx_cmd === cmd_writemem, state_mem_req,
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Mux(rx_cmd === cmd_readcr || rx_cmd === cmd_writecr, state_pcr_req,
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state_tx))
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}
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val mem_cnt = Reg(init=UInt(0, log2Up(REFILL_CYCLES)))
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val x_init = Module(new Queue(new Acquire, 1))
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when (state === state_mem_req && x_init.io.enq.ready) {
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state := Mux(cmd === cmd_writemem, state_mem_wdata, state_mem_rdata)
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}
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when (state === state_mem_wdata && io.mem.acquire.data.ready) {
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when (mem_cnt.andR) {
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state := state_mem_wresp
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}
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mem_cnt := mem_cnt + UInt(1)
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}
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when (state === state_mem_wresp) {
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when (mem_acked) {
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state := state_mem_finish
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mem_acked := Bool(false)
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}
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}
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when (state === state_mem_rdata) {
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when (io.mem.grant.valid) {
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when (mem_cnt.andR) {
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state := state_mem_finish
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}
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mem_cnt := mem_cnt + UInt(1)
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}
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mem_acked := Bool(false)
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}
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when (state === state_mem_finish && io.mem.grant_ack.ready) {
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state := Mux(cmd === cmd_readmem || pos === UInt(1), state_tx, state_rx)
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pos := pos - UInt(1)
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addr := addr + UInt(1 << OFFSET_BITS-3)
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}
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when (state === state_tx && tx_done) {
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when (tx_word_count === tx_size) {
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rx_count := UInt(0)
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tx_count := UInt(0)
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}
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state := Mux(cmd === cmd_readmem && pos != UInt(0), state_mem_req, state_rx)
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}
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var mem_req_data: Bits = null
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for (i <- 0 until MEM_DATA_BITS/short_request_bits) {
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val idx = Cat(mem_cnt, UInt(i, log2Up(MEM_DATA_BITS/short_request_bits)))
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when (state === state_mem_rdata && io.mem.grant.valid) {
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packet_ram(idx) := io.mem.grant.bits.payload.data((i+1)*short_request_bits-1, i*short_request_bits)
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}
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mem_req_data = Cat(packet_ram(idx), mem_req_data)
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}
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x_init.io.enq.valid := state === state_mem_req
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val init_addr = addr.toUInt >> UInt(OFFSET_BITS-3)
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x_init.io.enq.bits := Mux(cmd === cmd_writemem,
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Acquire(co.getUncachedWriteAcquireType, init_addr, UInt(0)),
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Acquire(co.getUncachedReadAcquireType, init_addr, UInt(0)))
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io.mem.acquire.meta <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq, UInt(conf.ln.nClients), UInt(0)) // By convention HTIF is the client with the largest id
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io.mem.acquire.data.valid := state === state_mem_wdata
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io.mem.acquire.data.bits.payload.data := mem_req_data
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io.mem.grant_ack.valid := (state === state_mem_finish) && mem_needs_ack
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io.mem.grant_ack.bits.payload.master_xact_id := mem_gxid
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io.mem.grant_ack.bits.header.dst := mem_gsrc
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io.mem.probe.ready := Bool(false)
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io.mem.release.meta.valid := Bool(false)
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io.mem.release.data.valid := Bool(false)
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val pcrReadData = Reg(Bits(width = io.cpu(0).pcr_rep.bits.getWidth))
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for (i <- 0 until nTiles) {
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val my_reset = Reg(init=Bool(true))
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val my_ipi = Reg(init=Bool(false))
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val cpu = io.cpu(i)
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val me = pcr_coreid === UInt(i)
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cpu.pcr_req.valid := state === state_pcr_req && me && pcr_addr != UInt(pcr_RESET)
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cpu.pcr_req.bits.rw := cmd === cmd_writecr
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cpu.pcr_req.bits.addr := pcr_addr
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cpu.pcr_req.bits.data := pcr_wdata
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cpu.reset := my_reset
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when (cpu.ipi_rep.ready) {
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my_ipi := Bool(false)
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}
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cpu.ipi_rep.valid := my_ipi
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cpu.ipi_req.ready := Bool(true)
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for (j <- 0 until nTiles) {
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when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UInt(i)) {
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my_ipi := Bool(true)
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}
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}
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when (cpu.pcr_req.valid && cpu.pcr_req.ready) {
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state := state_pcr_resp
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}
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when (state === state_pcr_req && me && pcr_addr === UInt(pcr_RESET)) {
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when (cmd === cmd_writecr) {
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my_reset := pcr_wdata(0)
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}
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pcrReadData := my_reset.toBits
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state := state_tx
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}
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cpu.pcr_rep.ready := Bool(true)
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when (cpu.pcr_rep.valid) {
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pcrReadData := cpu.pcr_rep.bits
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state := state_tx
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}
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}
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val scr_addr = addr(log2Up(nSCR)-1, 0)
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val scr_rdata = Vec.fill(io.scr.rdata.size){Bits(width = 64)}
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for (i <- 0 until scr_rdata.size)
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scr_rdata(i) := io.scr.rdata(i)
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scr_rdata(0) := UInt(nTiles)
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scr_rdata(1) := UInt(((REFILL_CYCLES*MEM_DATA_BITS/8) << x_init.io.enq.bits.addr.getWidth) >> 20)
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io.scr.wen := Bool(false)
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io.scr.wdata := pcr_wdata
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io.scr.waddr := scr_addr.toUInt
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when (state === state_pcr_req && pcr_coreid === SInt(-1)) {
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io.scr.wen := cmd === cmd_writecr
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pcrReadData := scr_rdata(scr_addr)
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state := state_tx
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}
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val tx_cmd = Mux(nack, cmd_nack, cmd_ack)
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val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd)
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val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext)
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val tx_data = Mux(tx_word_count === UInt(0), tx_header,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcrReadData,
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packet_ram(packet_ram_raddr)))
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io.host.in.ready := state === state_rx
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io.host.out.valid := state === state_tx
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io.host.out.bits := tx_data >> Cat(tx_count(log2Up(short_request_bits/w)-1,0), Bits(0, log2Up(w)))
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}
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