bug fix
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@ -466,7 +466,7 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module
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val ram_addr = Reg(Bits())
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val ram_out_valid = Reg(Bool())
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ram_out_valid := Bool(false)
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when (do_enq) { ram(enq_ptr) := io.enq.bits.toBits }
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when (do_enq) { ram(enq_ptr) := io.enq.bits }
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when (io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)) {
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ram_out_valid := Bool(true)
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ram_addr := Mux(io.deq.valid, deq_ptr + UInt(1), deq_ptr)
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