DRAMSideLLCLike trait. TSHRFile. New L2 config objects.
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@ -1,7 +1,7 @@
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package uncore
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import Chisel._
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abstract class CacheConfig {
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trait CacheConfig {
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def sets: Int
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def ways: Int
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def tl: TileLinkConfiguration
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@ -18,12 +18,16 @@ abstract class CacheConfig {
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def statebits: Int
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}
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case class L2CacheConfig(val sets: Int, val ways: Int,
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nReleaseTransactions: Int, nAcquireTransactions: Int,
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nrpq: Int, nsdq: Int,
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val tl: TileLinkConfiguration,
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val as: AddressSpaceConfiguration) extends CacheConfig {
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def databits = tl.dataBits
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case class L2CacheConfig(
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val sets: Int, val ways: Int,
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val nrpq: Int, val nsdq: Int,
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val nReleaseTransactions: Int,
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val nAcquireTransactions: Int,
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val tl: TileLinkConfiguration,
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val as: AddressSpaceConfiguration)
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extends CoherenceAgentConfiguration
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with CacheConfig
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{
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def states = tl.co.nMasterStates
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def lines = sets*ways
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def dm = ways == 1
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@ -33,8 +37,9 @@ case class L2CacheConfig(val sets: Int, val ways: Int,
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def waybits = log2Up(ways)
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def untagbits = offbits + idxbits
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def tagbits = lineaddrbits - idxbits
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def databytes = databits/8
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def wordoffbits = log2Up(databytes)
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def wordbits = 64
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def wordbytes = wordbits/8
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def wordoffbits = log2Up(wordbytes)
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def rowbits = tl.dataBits
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def rowbytes = rowbits/8
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def rowoffbits = log2Up(rowbytes)
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@ -45,17 +50,17 @@ case class L2CacheConfig(val sets: Int, val ways: Int,
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require(states > 0)
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require(isPow2(sets))
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require(isPow2(ways)) // TODO: relax this
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require(rowbits == tl.dataBits) //TODO: relax this?
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require(refillcycles == 1) //TODO: relax this?
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}
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abstract trait CacheBundle extends Bundle {
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implicit val conf: CacheConfig
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override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
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implicit val cacheconf: CacheConfig
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override def clone = this.getClass.getConstructors.head.newInstance(cacheconf).asInstanceOf[this.type]
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}
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abstract trait L2CacheBundle extends Bundle {
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implicit val conf: L2CacheConfig
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override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
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implicit val l2cacheconf: L2CacheConfig
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override def clone = this.getClass.getConstructors.head.newInstance(l2cacheconf).asInstanceOf[this.type]
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}
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abstract class ReplacementPolicy {
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@ -64,31 +69,31 @@ abstract class ReplacementPolicy {
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def hit: Unit
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}
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class RandomReplacement(implicit val conf: CacheConfig) extends ReplacementPolicy {
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class RandomReplacement(implicit val cacheconf: CacheConfig) extends ReplacementPolicy {
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private val replace = Bool()
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replace := Bool(false)
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val lfsr = LFSR16(replace)
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def way = if(conf.dm) UInt(0) else lfsr(log2Up(conf.ways)-1,0)
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def way = if(cacheconf.dm) UInt(0) else lfsr(log2Up(cacheconf.ways)-1,0)
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def miss = replace := Bool(true)
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def hit = {}
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}
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object MetaData {
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def apply(tag: Bits, state: UInt)(implicit conf: CacheConfig) = {
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def apply(tag: Bits, state: UInt)(implicit cacheconf: CacheConfig) = {
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val meta = new MetaData
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meta.state := state
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meta.tag := tag
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meta
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}
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}
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class MetaData(implicit val conf: CacheConfig) extends CacheBundle {
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val state = UInt(width = conf.statebits)
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val tag = Bits(width = conf.tagbits)
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class MetaData(implicit val cacheconf: CacheConfig) extends CacheBundle {
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val state = UInt(width = cacheconf.statebits)
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val tag = Bits(width = cacheconf.tagbits)
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}
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class MetaReadReq(implicit val conf: CacheConfig) extends CacheBundle {
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val idx = Bits(width = conf.idxbits)
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class MetaReadReq(implicit val cacheconf: CacheConfig) extends CacheBundle {
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val idx = Bits(width = cacheconf.idxbits)
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}
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class MetaWriteReq(implicit conf: CacheConfig) extends MetaReadReq()(conf) {
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@ -128,27 +133,26 @@ class MetaDataArray(implicit conf: CacheConfig) extends Module {
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io.write.ready := !rst
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}
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class L2DataReadReq(implicit val conf: L2CacheConfig) extends L2CacheBundle {
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val way_en = Bits(width = conf.ways)
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val addr = Bits(width = conf.untagbits)
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class L2DataReadReq(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle {
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val way_en = Bits(width = l2cacheconf.ways)
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val addr = Bits(width = l2cacheconf.tl.addrBits)
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}
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class L2DataWriteReq(implicit conf: L2CacheConfig) extends L2DataReadReq()(conf) {
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val wmask = Bits(width = conf.tl.writeMaskBits)
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val data = Bits(width = conf.rowbits)
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val data = Bits(width = conf.tl.dataBits)
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}
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class L2DataArray(implicit conf: L2CacheConfig) extends Module {
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val io = new Bundle {
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val read = Decoupled(new L2DataReadReq).flip
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val write = Decoupled(new L2DataWriteReq).flip
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val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.rowbits)}
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val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.tl.dataBits)}
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}
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val waddr = io.write.bits.addr >> UInt(conf.rowoffbits)
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val raddr = io.read.bits.addr >> UInt(conf.rowoffbits)
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val wmask = FillInterleaved(conf.databits, io.write.bits.wmask)
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val waddr = io.write.bits.addr
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val raddr = io.read.bits.addr
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val wmask = FillInterleaved(conf.wordbits, io.write.bits.wmask)
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for (w <- 0 until conf.ways) {
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val array = Mem(Bits(width=conf.rowbits), conf.sets*conf.refillcycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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@ -161,11 +165,51 @@ class L2DataArray(implicit conf: L2CacheConfig) extends Module {
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io.write.ready := Bool(true)
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}
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class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceAgent()(conf.tl)
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{
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trait InternalRequestState extends CacheBundle {
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val tag_match = Bool()
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val old_meta = new MetaData
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val way_en = Bits(width = cacheconf.ways)
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}
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class InternalAcquire(implicit val cacheconf: CacheConfig) extends Acquire()(cacheconf.tl)
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with InternalRequestState
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class InternalRelease(implicit val cacheconf: CacheConfig) extends Release()(cacheconf.tl)
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with InternalRequestState
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class InternalTileLinkIO(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle {
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implicit val (tl, ln) = (l2cacheconf.tl, l2cacheconf.tl.ln)
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val acquire = new DecoupledIO(new LogicalNetworkIO(new InternalAcquire))
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val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip
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val release = new DecoupledIO(new LogicalNetworkIO(new InternalRelease))
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val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
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val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
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}
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class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceAgent {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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// Create SHRs for outstanding transactions
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val tshrfile = Module(new TSHRFile(bankId))
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io.client <> tshrfile.io.client
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io.master <> tshrfile.io.outer
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io.incoherent <> tshrfile.io.incoherent
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}
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class TSHRFile(bankId: Int)(implicit conf: L2CacheConfig) extends Module {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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val io = new Bundle {
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val client = (new InternalTileLinkIO).flip
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val outer = new UncachedTileLinkIO
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val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
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val meta_read_req = Decoupled(new MetaReadReq)
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val meta_write_req = Decoupled(new MetaWriteReq)
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val data_read_req = Decoupled(new MetaReadReq)
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val data_write_req = Decoupled(new MetaWriteReq)
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}
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// Create TSHRs for outstanding transactions
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val nTrackers = conf.nReleaseTransactions + conf.nAcquireTransactions
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val trackerList = (0 until conf.nReleaseTransactions).map(id => Module(new L2VoluntaryReleaseTracker(id, bankId))) ++
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(conf.nReleaseTransactions until nTrackers).map(id => Module(new L2AcquireTracker(id, bankId)))
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@ -222,7 +266,7 @@ class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceA
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// Create an arbiter for the one memory port
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val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size))
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.master }
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io.master <> outer_arb.io.out
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io.outer <> outer_arb.io.out
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}
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@ -343,13 +343,15 @@ class MemReqArb(n: Int, refill_cycles: Int)(implicit conf: MemoryIFConfiguration
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when (unlock) { lock := Bool(false) }
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}
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class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, refill_cycles: Int, tagLeaf: Mem[UInt], dataLeaf: Mem[UInt])(implicit conf: MemoryIFConfiguration) extends Module
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{
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abstract class DRAMSideLLCLike(implicit conf: MemoryIFConfiguration) extends Module {
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val io = new Bundle {
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val cpu = new MemIO().flip
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val mem = new MemPipeIO
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}
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}
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class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, refill_cycles: Int, tagLeaf: Mem[UInt], dataLeaf: Mem[UInt])(implicit conf: MemoryIFConfiguration) extends DRAMSideLLCLike
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{
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val tagWidth = conf.addrBits - log2Up(sets)
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val metaWidth = tagWidth + 2 // valid + dirty
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@ -497,12 +499,8 @@ object HellaQueue
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}
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}
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class DRAMSideLLCNull(numRequests: Int, refillCycles: Int)(implicit conf: MemoryIFConfiguration) extends Module
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{
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val io = new Bundle {
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val cpu = new MemIO().flip
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val mem = new MemPipeIO
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}
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class DRAMSideLLCNull(numRequests: Int, refillCycles: Int)(implicit conf: MemoryIFConfiguration)
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extends DRAMSideLLCLike {
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val numEntries = numRequests * refillCycles
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val size = log2Down(numEntries) + 1
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@ -1,18 +1,27 @@
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package uncore
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import Chisel._
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abstract class CoherenceAgent(implicit conf: TileLinkConfiguration) extends Module {
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trait CoherenceAgentConfiguration {
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def tl: TileLinkConfiguration
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def nReleaseTransactions: Int
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def nAcquireTransactions: Int
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}
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abstract class CoherenceAgent(implicit conf: CoherenceAgentConfiguration) extends Module {
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val io = new Bundle {
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val client = (new TileLinkIO).flip
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val master = new UncachedTileLinkIO
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val incoherent = Vec.fill(conf.ln.nClients){Bool()}.asInput
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val client = (new TileLinkIO()(conf.tl)).flip
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val master = new UncachedTileLinkIO()(conf.tl)
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val incoherent = Vec.fill(conf.tl.ln.nClients){Bool()}.asInput
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}
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}
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case class L2CoherenceAgentConfiguration(tl: TileLinkConfiguration, nReleaseTransactions: Int, nAcquireTransactions: Int)
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case class L2CoherenceAgentConfiguration(
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val tl: TileLinkConfiguration,
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val nReleaseTransactions: Int,
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val nAcquireTransactions: Int) extends CoherenceAgentConfiguration
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class L2CoherenceAgent(bankId: Int)(implicit conf: L2CoherenceAgentConfiguration) extends CoherenceAgent()(conf.tl)
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{
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class L2CoherenceAgent(bankId: Int)(implicit conf: CoherenceAgentConfiguration)
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extends CoherenceAgent {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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// Create SHRs for outstanding transactions
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@ -76,7 +85,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: L2CoherenceAgentConfiguration
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}
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abstract class XactTracker()(implicit conf: L2CoherenceAgentConfiguration) extends Module {
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abstract class XactTracker()(implicit conf: CoherenceAgentConfiguration) extends Module {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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val io = new Bundle {
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val client = (new TileLinkIO).flip
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@ -94,7 +103,8 @@ abstract class XactTracker()(implicit conf: L2CoherenceAgentConfiguration) exten
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}
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class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgentConfiguration) extends XactTracker()(conf) {
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class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: CoherenceAgentConfiguration)
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extends XactTracker()(conf) {
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val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_idle)
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val xact = Reg{ new Release }
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@ -143,7 +153,8 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: L2Cohe
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}
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}
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class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgentConfiguration) extends XactTracker()(conf) {
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class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: CoherenceAgentConfiguration)
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extends XactTracker()(conf) {
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val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_busy :: Nil = Enum(UInt(), 6)
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val state = Reg(init=s_idle)
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val xact = Reg{ new Acquire }
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