cleanup mergeData and prep for cleaner data_buffer in L2
This commit is contained in:
Henry Cook
parent
b4ed1d9121
commit
059575c334
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@ -6,15 +6,16 @@ import Chisel._
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case object CacheName extends Field[String]
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case object NSets extends Field[Int]
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case object NWays extends Field[Int]
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case object BlockOffBits extends Field[Int]
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case object RowBits extends Field[Int]
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case object Replacer extends Field[() => ReplacementPolicy]
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case object AmoAluOperandBits extends Field[Int]
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case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
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case object CacheBlockBytes extends Field[Int]
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case object CacheBlockOffsetBits extends Field[Int]
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abstract trait CacheParameters extends UsesParameters {
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val nSets = params(NSets)
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val blockOffBits = params(BlockOffBits)
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val blockOffBits = params(CacheBlockOffsetBits)
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val idxBits = log2Up(nSets)
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val untagBits = blockOffBits + idxBits
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val tagBits = params(PAddrBits) - untagBits
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@ -165,6 +166,7 @@ abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgen
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val blockAddrBits = params(TLBlockAddrBits)
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val refillCyclesPerBeat = outerDataBits/rowBits
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val refillCycles = refillCyclesPerBeat*outerDataBeats
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val internalDataBeats = params(CacheBlockBytes)*8/rowBits
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require(refillCyclesPerBeat == 1)
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val amoAluOperandBits = params(AmoAluOperandBits)
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require(amoAluOperandBits <= innerDataBits)
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@ -410,6 +412,14 @@ class L2XactTrackerIO extends HierarchicalXactTrackerIO {
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}
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abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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class CacheBlockBuffer {
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val buffer = Reg(Bits(width = params(CacheBlockBytes)*8))
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def internal = Vec.fill(internalDataBeats){ Bits(width = rowBits) }.fromBits(buffer)
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def inner = Vec.fill(innerDataBeats){ Bits(width = innerDataBits) }.fromBits(buffer)
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def outer = Vec.fill(outerDataBeats){ Bits(width = outerDataBits) }.fromBits(buffer)
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}
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def connectDataBeatCounter[S <: L2HellaCacheBundle](inc: Bool, data: S, beat: UInt, full_block: Bool) = {
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if(data.refillCycles > 1) {
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val (multi_cnt, multi_done) = Counter(full_block && inc, data.refillCycles)
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@ -554,9 +564,10 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val xact_src = Reg(io.inner.acquire.bits.header.src.clone)
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val xact = Reg(Bundle(new Acquire, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
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val data_buffer = Vec.fill(innerDataBeats+1) { // Extra entry holds AMO result
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val data_buffer = Vec.fill(innerDataBeats) {
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Reg(io.iacq().data.clone)
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}
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}
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val amo_result = Reg(io.iacq().data.clone)
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val xact_tag_match = Reg{ Bool() }
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val xact_meta = Reg{ new L2Metadata }
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val xact_way_en = Reg{ Bits(width = nWays) }
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@ -612,44 +623,31 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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amoalu.io.cmd := xact.op_code()
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amoalu.io.typ := xact.op_size()
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amoalu.io.lhs := io.data.resp.bits.data //default
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amoalu.io.rhs := data_buffer(0) // default
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amoalu.io.rhs := data_buffer.head // default
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// TODO: figure out how to merge the following three versions of this func
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def mergeDataInternal[T <: HasL2Data](buffer: Vec[UInt], incoming: T) {
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val old_data = incoming.data
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val new_data = buffer(incoming.addr_beat)
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def mergeData[T <: HasTileLinkData]
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(byteAddrBits: Int, dataBits: Int)
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(buffer: Vec[UInt], beat: UInt, incoming: UInt) {
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val old_data = incoming
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val new_data = buffer(beat)
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val amoOpSz = UInt(amoAluOperandBits)
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val offset = xact.addr_byte()(innerByteAddrBits-1, log2Up(amoAluOperandBits/8))
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val offset = xact.addr_byte()(byteAddrBits-1, log2Up(amoAluOperandBits/8))
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amoalu.io.lhs := old_data >> offset*amoOpSz
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amoalu.io.rhs := new_data >> offset*amoOpSz
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val wmask =
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val valid_beat = xact.addr_beat === beat
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val wmask = Fill(dataBits, valid_beat) &
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Mux(xact.is(Acquire.putAtomicType),
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FillInterleaved(amoAluOperandBits, UIntToOH(offset)),
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Mux(xact.is(Acquire.putBlockType) || xact.is(Acquire.putType),
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FillInterleaved(8, xact.write_mask()),
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UInt(0, width = innerDataBits)))
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buffer(incoming.addr_beat) := ~wmask & old_data | wmask &
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UInt(0, width = dataBits)))
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buffer(beat) := ~wmask & old_data | wmask &
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Mux(xact.is(Acquire.putAtomicType), amoalu.io.out << offset*amoOpSz, new_data)
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when(xact.is(Acquire.putAtomicType)) { buffer(innerDataBeats) := old_data } // For AMO result
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}
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def mergeDataInner[T <: HasTileLinkData](buffer: Vec[UInt], incoming: T) = mergeDataOuter(buffer, incoming)
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def mergeDataOuter[T <: HasTileLinkData](buffer: Vec[UInt], incoming: T) {
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val old_data = incoming.data
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val new_data = buffer(incoming.addr_beat)
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val amoOpSz = UInt(amoAluOperandBits)
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val offset = xact.addr_byte()(innerByteAddrBits-1, log2Up(amoAluOperandBits/8))
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amoalu.io.lhs := old_data >> offset*amoOpSz
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amoalu.io.rhs := new_data >> offset*amoOpSz
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val wmask =
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Mux(xact.is(Acquire.putAtomicType),
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FillInterleaved(amoAluOperandBits, UIntToOH(offset)),
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Mux(xact.is(Acquire.putBlockType) || xact.is(Acquire.putType),
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FillInterleaved(8, xact.write_mask()),
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UInt(0, width = innerDataBits)))
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buffer(incoming.addr_beat) := ~wmask & old_data | wmask &
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Mux(xact.is(Acquire.putAtomicType), amoalu.io.out << offset*amoOpSz, new_data)
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when(xact.is(Acquire.putAtomicType)) { buffer(innerDataBeats) := old_data } // For AMO result
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when(xact.is(Acquire.putAtomicType) && valid_beat) { amo_result := old_data }
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}
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val mergeDataInternal = mergeData(log2Up(rowBits/8), rowBits) _
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val mergeDataInner = mergeData(innerByteAddrBits, innerDataBits) _
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val mergeDataOuter = mergeData(outerByteAddrBits, outerDataBits) _
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//TODO: Allow hit under miss for stores
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val in_same_set = xact.addr_block(idxMSB,idxLSB) ===
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@ -694,7 +692,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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manager_xact_id = UInt(trackerId),
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addr_beat = ignt_data_cnt,
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data = Mux(xact.is(Acquire.putAtomicType),
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data_buffer(innerDataBeats),
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amo_result,
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data_buffer(ignt_data_cnt)))
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io.inner.acquire.ready := Bool(false)
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@ -803,7 +801,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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when(io.irel().hasData()) {
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irel_had_data := Bool(true)
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pending_coh.outer := pending_ocoh_on_irel
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mergeDataInner(data_buffer, io.irel())
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mergeDataInner(data_buffer, io.irel().addr_beat, io.irel().data)
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}
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// We don't decrement release_count until we've received all the data beats.
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when(!io.irel().hasMultibeatData() || irel_data_done) {
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@ -824,7 +822,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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io.outer.grant.ready := Bool(true)
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when(io.outer.grant.valid) {
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when(io.ognt().hasData()) {
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mergeDataOuter(data_buffer, io.ognt())
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mergeDataOuter(data_buffer, io.ognt().addr_beat, io.ognt().data)
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ognt_had_data := Bool(true)
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}
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when(ognt_data_done) {
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@ -851,13 +849,13 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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is(s_data_read) {
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io.data.read.valid := !collect_iacq_data || iacq_data_valid(read_data_cnt)
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when(io.data.resp.valid) {
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mergeDataInternal(data_buffer, io.data.resp.bits)
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mergeDataInternal(data_buffer, io.data.resp.bits.addr_beat, io.data.resp.bits.data)
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}
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when(read_data_done) { state := s_data_resp }
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}
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is(s_data_resp) {
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when(io.data.resp.valid) {
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mergeDataInternal(data_buffer, io.data.resp.bits)
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mergeDataInternal(data_buffer, io.data.resp.bits.addr_beat, io.data.resp.bits.data)
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}
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when(resp_data_done) {
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state := Mux(xact.hasData(), s_data_write, s_inner_grant)
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@ -21,6 +21,8 @@ trait CoherenceAgentParameters extends UsesParameters {
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def outerTLParams = params.alterPartial({ case TLId => params(OuterTLId)})
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val outerDataBeats = outerTLParams(TLDataBeats)
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val outerDataBits = outerTLParams(TLDataBits)
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val outerBeatAddrBits = log2Up(outerDataBeats)
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val outerByteAddrBits = log2Up(outerDataBits/8)
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def innerTLParams = params.alterPartial({case TLId => params(InnerTLId)})
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val innerDataBeats = innerTLParams(TLDataBeats)
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val innerDataBits = innerTLParams(TLDataBits)
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