Cache utility traits. Completely compiles, asm tests hang.
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@ -3,17 +3,35 @@ import Chisel._
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case object NSets extends Field[Int]
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case object NWays extends Field[Int]
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case object IsDM extends Field[Boolean]
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case object TagBits extends Field[Int]
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case object IdxBits extends Field[Int]
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case object OffBits extends Field[Int]
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case object UntagBits extends Field[Int]
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case object WayBits extends Field[Int]
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case object BlockOffBits extends Field[Int]
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case object RowBits extends Field[Int]
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case object WordBits extends Field[Int]
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case object RefillCycles extends Field[Int]
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case object Replacer extends Field[() => ReplacementPolicy]
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abstract trait CacheParameters extends UsesParameters {
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val paddrBits = params(PAddrBits)
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val vaddrBits = params(VAddrBits)
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val pgIdxBits = params(PgIdxBits)
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val nSets = params(NSets)
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val nWays = params(NWays)
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val blockOffBits = params(BlockOffBits)
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val wordBits = params(WordBits)
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val rowBits = params(RowBits)
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val wordOffBits = log2Up(wordBits)
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val idxBits = log2Up(nSets)
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val untagBits = blockOffBits + idxBits
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val tagBits = paddrBits - untagBits
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val wayBits = log2Up(nWays)
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val isDM = nWays == 1
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val rowWords = rowBits/wordBits
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val rowBytes = rowBits*8
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val rowOffBits = log2Up(rowBytes)
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val refillCycles = params(TLDataBits)/rowBits
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}
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abstract class CacheBundle extends Bundle with CacheParameters
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abstract class CacheModule extends Module with CacheParameters
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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@ -30,43 +48,43 @@ class RandomReplacement(ways: Int) extends ReplacementPolicy {
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def hit = {}
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}
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abstract class Metadata extends Bundle {
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val tag = Bits(width = params(TagBits))
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abstract class Metadata extends CacheBundle {
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val tag = Bits(width = tagBits)
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val coh: CoherenceMetadata
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}
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class MetaReadReq extends Bundle {
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val idx = Bits(width = params(IdxBits))
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class MetaReadReq extends CacheBundle {
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val idx = Bits(width = idxBits)
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}
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class MetaWriteReq[T <: Metadata](gen: T) extends MetaReadReq {
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val way_en = Bits(width = params(WayBits))
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val way_en = Bits(width = nWays)
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val data = gen.clone
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override def clone = new MetaWriteReq(gen).asInstanceOf[this.type]
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}
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class MetadataArray[T <: Metadata](makeRstVal: () => T) extends Module {
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class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
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val rstVal = makeRstVal()
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val io = new Bundle {
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val read = Decoupled(new MetaReadReq).flip
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val write = Decoupled(new MetaWriteReq(rstVal.clone)).flip
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val resp = Vec.fill(params(NWays)){rstVal.clone.asOutput}
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val resp = Vec.fill(nWays){rstVal.clone.asOutput}
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}
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val metabits = rstVal.getWidth
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val rst_cnt = Reg(init=UInt(0, log2Up(params(NSets)+1)))
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val rst = rst_cnt < UInt(params(NSets))
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val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
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val rst = rst_cnt < UInt(nSets)
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val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
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val wdata = Mux(rst, rstVal, io.write.bits.data).toBits
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val wmask = Mux(rst, SInt(-1), io.write.bits.way_en)
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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val tag_arr = Mem(UInt(width = metabits*params(NWays)), params(NSets), seqRead = true)
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val tag_arr = Mem(UInt(width = metabits*nWays), nSets, seqRead = true)
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when (rst || io.write.valid) {
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tag_arr.write(waddr, Fill(params(NWays), wdata), FillInterleaved(metabits, wmask))
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tag_arr.write(waddr, Fill(nWays, wdata), FillInterleaved(metabits, wmask))
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}
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val tags = tag_arr(RegEnable(io.read.bits.idx, io.read.valid))
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for (w <- 0 until params(NWays)) {
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for (w <- 0 until nWays) {
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val m = tags(metabits*(w+1)-1, metabits*w)
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io.resp(w) := rstVal.clone.fromBits(m)
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}
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@ -75,14 +93,20 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends Module {
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io.write.ready := !rst
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}
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trait HasL2Id extends Bundle {
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val id = UInt(width = log2Up(params(NTransactors)))
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abstract trait L2HellaCacheParameters extends CacheParameters
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with CoherenceAgentParameters
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters
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trait HasL2Id extends Bundle with CoherenceAgentParameters {
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val id = UInt(width = log2Up(nTransactors))
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}
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trait HasL2InternalRequestState extends Bundle {
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trait HasL2InternalRequestState extends L2HellaCacheBundle {
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val tag_match = Bool()
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val old_meta = new L2Metadata
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val way_en = Bits(width = params(NWays))
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val way_en = Bits(width = nWays)
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}
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object L2Metadata {
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@ -93,23 +117,22 @@ object L2Metadata {
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meta
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}
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}
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class L2Metadata extends Metadata {
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val coh = params(TLCoherence).masterMetadataOnFlush.clone
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class L2Metadata extends Metadata with L2HellaCacheParameters {
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val coh = co.masterMetadataOnFlush.clone
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}
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class L2MetaReadReq extends MetaReadReq with HasL2Id {
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val tag = Bits(width = params(TagBits))
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val tag = Bits(width = tagBits)
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}
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class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata)
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with HasL2Id
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class L2MetaResp extends Bundle
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class L2MetaResp extends L2HellaCacheBundle
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with HasL2Id
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with HasL2InternalRequestState
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class L2MetadataArray extends Module {
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val (co, ways) = (params(TLCoherence), params(NWays))
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class L2MetadataArray extends L2HellaCacheModule {
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val io = new Bundle {
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val read = Decoupled(new L2MetaReadReq).flip
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val write = Decoupled(new L2MetaWriteReq).flip
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@ -123,7 +146,7 @@ class L2MetadataArray extends Module {
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val s1_clk_en = Reg(next = io.read.fire())
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val s1_tag = RegEnable(io.read.bits.tag, io.read.valid)
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val s1_id = RegEnable(io.read.bits.id, io.read.valid)
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def wayMap[T <: Data](f: Int => T) = Vec((0 until ways).map(f))
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def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
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val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
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val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && co.isValid(meta.io.resp(w).coh)).toBits
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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@ -146,8 +169,8 @@ class L2MetadataArray extends Module {
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io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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}
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class L2DataReadReq extends Bundle with HasL2Id {
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val way_en = Bits(width = params(NWays))
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class L2DataReadReq extends L2HellaCacheBundle with HasL2Id {
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val way_en = Bits(width = nWays)
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val addr = Bits(width = params(TLAddrBits))
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}
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@ -160,7 +183,7 @@ class L2DataResp extends Bundle with HasL2Id {
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val data = Bits(width = params(TLDataBits))
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}
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class L2DataArray extends Module {
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class L2DataArray extends L2HellaCacheModule {
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val io = new Bundle {
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val read = Decoupled(new L2DataReadReq).flip
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val write = Decoupled(new L2DataWriteReq).flip
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@ -169,9 +192,9 @@ class L2DataArray extends Module {
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val waddr = io.write.bits.addr
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val raddr = io.read.bits.addr
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val wmask = FillInterleaved(params(WordBits), io.write.bits.wmask)
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val resp = (0 until params(NWays)).map { w =>
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val array = Mem(Bits(width=params(RowBits)), params(NSets)*params(RefillCycles), seqRead = true)
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val wmask = FillInterleaved(wordBits, io.write.bits.wmask)
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val resp = (0 until nWays).map { w =>
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val array = Mem(Bits(width=params(RowBits)), nSets*refillCycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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@ -185,11 +208,11 @@ class L2DataArray extends Module {
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io.write.ready := Bool(true)
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}
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class L2HellaCache(bankId: Int) extends CoherenceAgent {
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class L2HellaCache(bankId: Int) extends CoherenceAgent with L2HellaCacheParameters {
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require(isPow2(params(NSets)))
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require(isPow2(params(NWays)))
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require(params(RefillCycles) == 1)
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require(isPow2(nSets))
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require(isPow2(nWays))
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require(refillCycles == 1)
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val tshrfile = Module(new TSHRFile(bankId))
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val meta = Module(new L2MetadataArray)
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@ -207,8 +230,7 @@ class L2HellaCache(bankId: Int) extends CoherenceAgent {
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}
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class TSHRFile(bankId: Int) extends Module {
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val (co, nClients) = (params(TLCoherence), params(NClients))
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class TSHRFile(bankId: Int) extends L2HellaCacheModule {
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val io = new Bundle {
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val inner = (new TileLinkIO).flip
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val outer = new UncachedTileLinkIO
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@ -234,9 +256,9 @@ class TSHRFile(bankId: Int) extends Module {
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}
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// Create TSHRs for outstanding transactions
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val trackerList = (0 until params(NReleaseTransactors)).map { id =>
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val trackerList = (0 until nReleaseTransactors).map { id =>
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Module(new L2VoluntaryReleaseTracker(id, bankId))
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} ++ (params(NReleaseTransactors) until params(NTransactors)).map { id =>
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} ++ (nReleaseTransactors until nTransactors).map { id =>
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Module(new L2AcquireTracker(id, bankId))
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}
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@ -301,8 +323,7 @@ class TSHRFile(bankId: Int) extends Module {
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}
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abstract class L2XactTracker extends Module {
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val (co, nClients) = (params(TLCoherence),params(NClients))
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abstract class L2XactTracker extends L2HellaCacheModule {
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val io = new Bundle {
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val inner = (new TileLinkIO).flip
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val outer = new UncachedTileLinkIO
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@ -209,7 +209,7 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int) extends Module {
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val co = params(TLCoherence)
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val tbits = params(MIFTagBits)
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val dbits = params(MIFDataBits)
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val dbeats = params(MIFDataBits)
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val dbeats = params(MIFDataBeats)
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require(params(TLDataBits) == dbits*dbeats)
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//require(params(TLClientXactIdBits) <= params(MIFTagBits))
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@ -3,24 +3,31 @@ import Chisel._
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case object NReleaseTransactors extends Field[Int]
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case object NAcquireTransactors extends Field[Int]
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case object NTransactors extends Field[Int]
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case object NClients extends Field[Int]
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abstract class CoherenceAgent extends Module {
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abstract trait CoherenceAgentParameters extends UsesParameters {
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val co = params(TLCoherence)
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val nReleaseTransactors = params(NReleaseTransactors)
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val nAcquireTransactors = params(NAcquireTransactors)
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val nTransactors = nReleaseTransactors + nAcquireTransactors
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val nClients = params(NClients)
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}
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abstract class CoherenceAgent extends Module
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with CoherenceAgentParameters {
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val io = new Bundle {
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val inner = (new TileLinkIO).flip
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val outer = new UncachedTileLinkIO
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val incoherent = Vec.fill(params(NClients)){Bool()}.asInput
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val incoherent = Vec.fill(nClients){Bool()}.asInput
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}
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}
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class L2CoherenceAgent(bankId: Int) extends CoherenceAgent {
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// Create SHRs for outstanding transactions
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val trackerList = (0 until params(NReleaseTransactors)).map(id =>
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val trackerList = (0 until nReleaseTransactors).map(id =>
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Module(new VoluntaryReleaseTracker(id, bankId))) ++
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(params(NReleaseTransactors) until params(NTransactors)).map(id =>
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(nReleaseTransactors until nTransactors).map(id =>
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Module(new AcquireTracker(id, bankId)))
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// Propagate incoherence flags
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