Merge branch 'l2-subblock-merging' of github.com:ucb-bar/uncore into l2-subblock-merging
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commit
b364d387de
@ -172,7 +172,6 @@ abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgen
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require(amoAluOperandBits <= innerDataBits)
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require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
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val nSecondaryMisses = 4
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val enableGetMerging = false
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}
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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@ -708,8 +707,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val mergeDataInner = mergeData(innerDataBits) _
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val mergeDataOuter = mergeData(outerDataBits) _
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val can_merge_iacq_get = Bool(enableGetMerging) &&
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(xact.isBuiltInType(Acquire.getType) &&
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val can_merge_iacq_get = (xact.isBuiltInType(Acquire.getType) &&
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io.iacq().isBuiltInType(Acquire.getType)) &&
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(xact_src === io.inner.acquire.bits.header.src) &&
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xact.conflicts(io.iacq()) &&
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@ -825,7 +823,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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xact.data := UInt(0)
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wmask_buffer.foreach { w => w := UInt(0) }
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pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
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UInt(0),
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addPendingBitWhenHasData(io.inner.acquire),
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SInt(-1, width = innerDataBeats)).toUInt
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pending_reads := Mux(io.iacq().isSubBlockType(),
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addPendingBitWhenWmaskIsNotFull(io.inner.acquire),
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@ -993,13 +991,15 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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}
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// Handle Get and Put merging
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when(io.inner.acquire.fire() && io.iacq().hasData()) {
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val beat = io.iacq().addr_beat
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val wmask = io.iacq().wmask()
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val full = FillInterleaved(8, wmask)
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data_buffer(beat) := (~full & data_buffer(beat)) | (full & io.iacq().data)
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wmask_buffer(beat) := wmask | Mux(state === s_idle, Bits(0), wmask_buffer(beat))
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when(!xact.hasMultibeatData()) { ignt_q.io.enq.valid := Bool(true) }
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when(io.inner.acquire.fire()) {
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when (io.iacq().hasData()) {
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val beat = io.iacq().addr_beat
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val wmask = io.iacq().wmask()
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val full = FillInterleaved(8, wmask)
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data_buffer(beat) := (~full & data_buffer(beat)) | (full & io.iacq().data)
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wmask_buffer(beat) := wmask | Mux(state === s_idle, Bits(0), wmask_buffer(beat))
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}
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when(!io.iacq().hasMultibeatData()) { ignt_q.io.enq.valid := Bool(true) }
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}
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assert(!(state != s_idle && io.inner.acquire.fire() &&
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