Use Vec.apply, not Vec.fill, for type nodes
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005752e2a6
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05d311c517
@ -40,7 +40,7 @@ class L2BroadcastHub extends ManagerCoherenceAgent
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trackerList.map(_.io.incoherent := io.incoherent)
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// Queue to store impending Put data
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val sdq = Reg(Vec.fill(sdqDepth){io.iacq().data})
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val sdq = Reg(Vec(io.iacq().data, sdqDepth))
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val sdq_val = Reg(init=Bits(0, sdqDepth))
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val sdq_alloc_id = PriorityEncoder(~sdq_val)
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val sdq_rdy = !sdq_val.andR
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@ -69,7 +69,7 @@ class L2BroadcastHub extends ManagerCoherenceAgent
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val voluntary = io.irel().isVoluntary()
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val vwbdq_enq = io.inner.release.fire() && voluntary && io.irel().hasData()
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val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, innerDataBeats) //TODO Zero width
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val vwbdq = Reg(Vec.fill(innerDataBeats){io.irel().data}) //TODO Assumes nReleaseTransactors == 1
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val vwbdq = Reg(Vec(io.irel().data, innerDataBeats)) //TODO Assumes nReleaseTransactors == 1
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when(vwbdq_enq) { vwbdq(rel_data_cnt) := io.irel().data }
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// Handle releases, which might be voluntary and might have data
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@ -131,7 +131,7 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int) extends BroadcastXactTrac
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val state = Reg(init=s_idle)
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val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
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val data_buffer = Reg(Vec.fill(innerDataBeats){io.irel().data})
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val data_buffer = Reg(Vec(io.irel().data, innerDataBeats))
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val coh = ManagerMetadata.onReset
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val collect_irel_data = Reg(init=Bool(false))
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@ -210,7 +210,7 @@ class BroadcastAcquireTracker(trackerId: Int) extends BroadcastXactTracker {
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val state = Reg(init=s_idle)
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val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
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val data_buffer = Reg(Vec.fill(innerDataBeats){io.iacq().data})
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val data_buffer = Reg(Vec(io.iacq().data, innerDataBeats))
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val coh = ManagerMetadata.onReset
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assert(!(state != s_idle && xact.isBuiltInType() &&
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@ -145,7 +145,7 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
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val io = new Bundle {
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val read = Decoupled(new MetaReadReq).flip
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val write = Decoupled(new MetaWriteReq(rstVal)).flip
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val resp = Vec.fill(nWays){rstVal.cloneType.asOutput}
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val resp = Vec(rstVal.cloneType.asOutput, nWays)
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}
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val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
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val rst = rst_cnt < UInt(nSets)
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@ -427,9 +427,9 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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class CacheBlockBuffer { // TODO
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val buffer = Reg(Bits(width = params(CacheBlockBytes)*8))
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def internal = Vec.fill(internalDataBeats){ Bits(width = rowBits) }.fromBits(buffer)
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def inner = Vec.fill(innerDataBeats){ Bits(width = innerDataBits) }.fromBits(buffer)
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def outer = Vec.fill(outerDataBeats){ Bits(width = outerDataBits) }.fromBits(buffer)
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def internal = Vec(Bits(width = rowBits), internalDataBeats).fromBits(buffer)
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def inner = Vec(Bits(width = innerDataBits), innerDataBeats).fromBits(buffer)
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def outer = Vec(Bits(width = outerDataBits), outerDataBeats).fromBits(buffer)
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}
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def connectDataBeatCounter[S <: L2HellaCacheBundle](inc: Bool, data: S, beat: UInt, full_block: Bool) = {
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@ -492,7 +492,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
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val state = Reg(init=s_idle)
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val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
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val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)})
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val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats))
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val xact_way_en = Reg{ Bits(width = nWays) }
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val xact_old_meta = Reg{ new L2Metadata }
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val coh = xact_old_meta.coh
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@ -587,8 +587,8 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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// State holding transaction metadata
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val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) }))
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val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)})
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val wmask_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits/8)})
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val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats))
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val wmask_buffer = Reg(init=Vec(UInt(0, width = innerDataBits/8), innerDataBeats))
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val xact_tag_match = Reg{ Bool() }
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val xact_way_en = Reg{ Bits(width = nWays) }
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val xact_old_meta = Reg{ new L2Metadata }
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@ -980,7 +980,7 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
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val state = Reg(init=s_idle)
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val xact = Reg(new L2WritebackReq)
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val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)})
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val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats))
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val xact_addr_block = Cat(xact.tag, xact.idx)
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val pending_irels =
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@ -51,7 +51,7 @@ class HTIFIO extends HTIFBundle {
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}
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class SCRIO extends HTIFBundle {
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val rdata = Vec.fill(nSCR){Bits(INPUT, 64)}
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val rdata = Vec(Bits(INPUT, 64), nSCR)
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val wen = Bool(OUTPUT)
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val waddr = UInt(OUTPUT, log2Up(nSCR))
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val wdata = Bits(OUTPUT, 64)
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@ -59,7 +59,7 @@ class SCRIO extends HTIFBundle {
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class HTIFModuleIO extends HTIFBundle {
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val host = new HostIO
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val cpu = Vec.fill(nCores){new HTIFIO}.flip
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val cpu = Vec(new HTIFIO, nCores).flip
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val mem = new ClientUncachedTileLinkIO
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val scr = new SCRIO
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}
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@ -18,8 +18,8 @@ class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle {
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}
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class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle {
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val in = Vec.fill(n){Decoupled(new PhysicalNetworkIO(n,dType))}.flip
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val out = Vec.fill(n){Decoupled(new PhysicalNetworkIO(n,dType))}
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val in = Vec(Decoupled(new PhysicalNetworkIO(n,dType)), n).flip
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val out = Vec(Decoupled(new PhysicalNetworkIO(n,dType)), n)
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}
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abstract class PhysicalNetwork extends Module
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@ -27,7 +27,7 @@ abstract class PhysicalNetwork extends Module
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class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork {
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val io = new BasicCrossbarIO(n, dType)
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val rdyVecs = List.fill(n){Vec.fill(n)(Wire(Bool()))}
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val rdyVecs = Seq.fill(n){Seq.fill(n)(Wire(Bool()))}
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io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock))
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@ -1086,7 +1086,7 @@ trait TileLinkArbiterLike extends TileLinkParameters {
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/** Abstract base case for any Arbiters that have UncachedTileLinkIOs */
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abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike {
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val io = new Bundle {
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val in = Vec.fill(arbN){new UncachedTileLinkIO}.flip
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val in = Vec(new UncachedTileLinkIO, arbN).flip
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val out = new UncachedTileLinkIO
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}
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hookupClientSource(io.in.map(_.acquire), io.out.acquire)
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@ -1097,7 +1097,7 @@ abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with Tile
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/** Abstract base case for any Arbiters that have cached TileLinkIOs */
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abstract class TileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike {
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val io = new Bundle {
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val in = Vec.fill(arbN){new TileLinkIO}.flip
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val in = Vec(new TileLinkIO, arbN).flip
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val out = new TileLinkIO
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}
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hookupClientSource(io.in.map(_.acquire), io.out.acquire)
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@ -1141,7 +1141,7 @@ class TileLinkIOArbiterThatUsesNewId(val n: Int) extends TileLinkIOArbiter(n) wi
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/** Concrete uncached client-side arbiter that appends the arbiter's port id to client_xact_id */
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class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId {
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val io = new Bundle {
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val in = Vec.fill(arbN){new ClientUncachedTileLinkIO}.flip
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val in = Vec(new ClientUncachedTileLinkIO, arbN).flip
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val out = new ClientUncachedTileLinkIO
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}
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hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
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@ -1151,7 +1151,7 @@ class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLin
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/** Concrete client-side arbiter that appends the arbiter's port id to client_xact_id */
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class ClientTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId {
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val io = new Bundle {
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val in = Vec.fill(arbN){new ClientTileLinkIO}.flip
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val in = Vec(new ClientTileLinkIO, arbN).flip
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val out = new ClientTileLinkIO
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}
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hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
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@ -1461,7 +1461,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
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val (mif_cnt_out, mif_wrap_out) = Counter(mem_data_q.io.enq.fire(), mifDataBeats)
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val mif_done_out = Reg(init=Bool(false))
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val tl_buf_out = Reg(Vec(io.tl.acquire.bits.data, tlDataBeats))
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val mif_buf_out = Vec.fill(mifDataBeats){ new MemData }
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val mif_buf_out = Vec(new MemData, mifDataBeats)
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mif_buf_out := mif_buf_out.fromBits(tl_buf_out.toBits)
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val mif_prog_out = (mif_cnt_out+UInt(1, width = log2Up(mifDataBeats+1)))*UInt(mifDataBits)
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val tl_prog_out = tl_cnt_out*UInt(tlDataBits)
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@ -1611,7 +1611,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
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val (mif_cnt_in, mif_wrap_in) = Counter(io.mem.resp.fire(), mifDataBeats) // TODO: Assumes all resps have data
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val mif_done_in = Reg(init=Bool(false))
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val mif_buf_in = Reg(Vec(new MemData, mifDataBeats))
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val tl_buf_in = Vec.fill(tlDataBeats){ io.tl.acquire.bits.data }
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val tl_buf_in = Vec(io.tl.acquire.bits.data, tlDataBeats)
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tl_buf_in := tl_buf_in.fromBits(mif_buf_in.toBits)
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val tl_prog_in = (tl_cnt_in+UInt(1, width = log2Up(tlDataBeats+1)))*UInt(tlDataBits)
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val mif_prog_in = mif_cnt_in*UInt(mifDataBits)
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@ -50,7 +50,7 @@ trait HasCoherenceAgentWiringHelpers {
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trait HasInnerTLIO extends CoherenceAgentBundle {
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val inner = Bundle(new ManagerTileLinkIO)(innerTLParams)
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val incoherent = Vec.fill(inner.tlNCachingClients){Bool()}.asInput
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val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput
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def iacq(dummy: Int = 0) = inner.acquire.bits
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def iprb(dummy: Int = 0) = inner.probe.bits
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def irel(dummy: Int = 0) = inner.release.bits
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@ -62,7 +62,7 @@ class FlowThroughSerializer[T <: HasTileLinkData](gen: T, n: Int) extends Module
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val rbits = Reg{io.in.bits}
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val active = Reg(init=Bool(false))
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val shifter = Vec.fill(n){Bits(width = narrowWidth)}
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val shifter = Vec(Bits(width = narrowWidth), n)
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(0 until n).foreach {
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i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth)
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}
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