Avoid type-unsafe assignments
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05d311c517
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@ -364,7 +364,7 @@ class TSHRFile extends L2HellaCacheModule with HasCoherenceAgentWiringHelpers {
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doInternalInputRouting(wb.io.wb.resp, trackerList.map(_.io.wb.resp))
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// Propagate incoherence flags
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(trackerList.map(_.io.incoherent) :+ wb.io.incoherent) foreach { _ := io.incoherent.toBits }
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(trackerList.map(_.io.incoherent) :+ wb.io.incoherent) foreach { _ := io.incoherent }
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// Handle acquire transaction initiation
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val trackerAcquireIOs = trackerList.map(_.io.inner.acquire)
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@ -525,7 +525,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
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io.data.write.bits.way_en := xact_way_en
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io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB)
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io.data.write.bits.addr_beat := curr_write_beat
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io.data.write.bits.wmask := SInt(-1)
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io.data.write.bits.wmask := ~UInt(0, io.data.write.bits.wmask.getWidth)
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io.data.write.bits.data := data_buffer(curr_write_beat)
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// Send an acknowledgement
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@ -663,7 +663,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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wmask & Mux(xact.isBuiltInType(Acquire.putAtomicType),
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amoalu.io.out << xact.amo_shift_bits(),
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new_data)
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wmask_buffer(beat) := SInt(-1)
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wmask_buffer(beat) := ~UInt(0, wmask_buffer.head.getWidth)
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when(xact.is(Acquire.putAtomicType) && xact.addr_beat === beat) { amo_result := old_data }
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}
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def mergeDataInternal[T <: HasL2Data with HasL2BeatAddr](in: ValidIO[T]) {
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@ -1057,7 +1057,7 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
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val coh = io.wb.req.bits.coh
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val needs_inner_probes = coh.inner.requiresProbesOnVoluntaryWriteback()
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when(needs_inner_probes) { pending_iprbs := coh.inner.full() & ~io.incoherent.toBits }
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pending_reads := SInt(-1, width = innerDataBeats)
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pending_reads := ~UInt(0, width = innerDataBeats)
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pending_resps := UInt(0)
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pending_orel_data := UInt(0)
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state := Mux(needs_inner_probes, s_inner_probe, s_busy)
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