first version NASTI IOs
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uncore/src/main/scala/nasti.scala
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89
uncore/src/main/scala/nasti.scala
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// See LICENSE for license details.
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package uncore
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import Chisel._
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case object NASTIDataBits extends Field[Int]
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case object NASTIAddrBits extends Field[Int]
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case object NASTIReadIdBits extends Field[Int]
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case object NASTIWriteIdBits extends Field[Int]
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trait NASTIParameters extends UsesParameters {
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val dataBits = params(NASTIDataBits)
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val strobeBits = dataBits / 8
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val addrBits = params(NASTIAddrBits)
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val widBits = params(NASTIWriteIdBits)
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val ridBits = params(NASTIReadIdBits)
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val userBits = 32
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val awUserBits = userBits
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val wUserBits = userBits
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val bUserBits = userBits
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val arUserBits = userBits
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val rUserBits = userBits
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}
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abstract class NASTIBundle extends Bundle with NASTIParameters
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abstract class NASTIModule extends Module with NASTIParameters
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trait NASTIChannel extends NASTIBundle
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trait NASTIMasterToSlaveChannel extends NASTIChannel
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trait NASTISlaveToMasterChannel extends NASTIChannel
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class NASTIMasterIO extends Bundle {
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val writeAddress = Decoupled(new NASTIaw)
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val writeData = Decoupled(new NASTIw)
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val writeResponse = Decoupled(new NASTIb).flip
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val readAddress = Decoupled(new NASTIar)
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val readData = Decoupled(new NASTIr).flip
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}
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class NASTISlaveIO extends NASTIMasterIO { flip() }
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class NASTIaw extends NASTIMasterToSlaveChannel {
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val awID = UInt(width = widBits)
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val awAddr = UInt(width = addrBits)
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val awLen = UInt(width = 8)
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val awSize = UInt(width = 3)
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val awBurst = UInt(width = 2)
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val awCache = UInt(width = 4)
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val awProt = UInt(width = 3)
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val awQOS = UInt(width = 4)
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val awRegion = UInt(width = 4)
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val awLock = Bool()
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val awUser = UInt(width = awUserBits)
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}
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class NASTIw extends NASTIMasterToSlaveChannel {
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val wData = UInt(width = dataBits)
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val wStrb = UInt(width = strobeBits)
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val wUser = UInt(width = wUserBits)
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val wLast = Bool()
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}
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class NASTIb extends NASTISlaveToMasterChannel {
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val bID = UInt(width = widBits)
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val bResp = UInt(width = 2)
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val bUser = UInt(width = bUserBits)
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}
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class NASTIar extends NASTIMasterToSlaveChannel {
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val arID = UInt(width = ridBits)
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val arAddr = UInt(width = addrBits)
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val arLen = UInt(width = 8)
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val arSize = UInt(width = 3)
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val arBurst = UInt(width = 2)
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val arCache = UInt(width = 4)
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val arQOS = UInt(width = 3)
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val arRegion = UInt(width = 4)
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val arProt = UInt(width = 4)
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val arLock = Bool()
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val arUser = UInt(width = arUserBits)
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}
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class NASTIr extends NASTISlaveToMasterChannel {
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val rID = UInt(width = ridBits)
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val rData = UInt(width = dataBits)
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val rResp = UInt(width = 2)
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val rUser = UInt(width = rUserBits)
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val rLast = Bool()
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}
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