riscv/rocket-chip
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get rid of non-NASTI RTC module

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This commit is contained in:
Howard Mao 2015-09-10 17:52:26 -07:00
parent 6ee6ea4f1e
commit 64717706a9
1 changed files with 0 additions and 32 deletions
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32
uncore/src/main/scala/rtc.scala
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@ -4,38 +4,6 @@ import Chisel._
import junctions.{NASTIMasterIO, NASTIAddrHashMap, SMIIO}
class RTC(pcr_MTIME: Int) extends Module {
private val nCores = params(HTIFNCores)
val io = new Bundle {
val smi = Vec.fill(nCores) { new SMIIO(64, 12) }
}
val rtc = Reg(init=UInt(0,64))
val rtc_tick = Counter(params(RTCPeriod)).inc()
for ((smi, i) <- io.smi.zipWithIndex) {
val rtc_sending = Reg(init = Bool(false))
val rtc_outstanding = Reg(init = Bool(false))
when (rtc_tick) {
rtc := rtc + UInt(1)
rtc_sending := Bool(true)
rtc_outstanding := Bool(true)
}
when (smi.req.fire()) { rtc_sending := Bool(false) }
when (smi.resp.fire()) { rtc_outstanding := Bool(false) }
assert(!rtc_tick || !rtc_outstanding, "Last rtc tick not yet sent")
smi.req.bits.addr := UInt(pcr_MTIME)
smi.req.bits.rw := Bool(true)
smi.req.bits.data := rtc
smi.req.valid := rtc_sending
smi.resp.ready := Bool(true)
}
}
class RTCNASTI(pcr_MTIME: Int) extends Module {
val io = new NASTIMasterIO
private val nCores = params(HTIFNCores)