Remove IPI network
This is now provided via MMIO.
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parent
0290635454
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d426ecee78
@ -41,8 +41,6 @@ class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
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val reset = Bool(INPUT)
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val id = UInt(INPUT, log2Up(nCores))
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val csr = new SMIIO(scrDataBits, 12).flip
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val ipi_req = Decoupled(Bits(width = log2Up(nCores)))
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val ipi_rep = Decoupled(Bool()).flip
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val debug_stats_csr = Bool(OUTPUT)
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// wired directly to stats register
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// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
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@ -176,7 +174,6 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
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val csrReadData = Reg(Bits(width = io.cpu(0).csr.resp.bits.getWidth))
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for (i <- 0 until nCores) {
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val my_reset = Reg(init=Bool(true))
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val my_ipi = Reg(init=Bool(false))
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val cpu = io.cpu(i)
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val me = csr_coreid === UInt(i)
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@ -186,17 +183,6 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
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cpu.csr.req.bits.data := csr_wdata
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cpu.reset := my_reset
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when (cpu.ipi_rep.ready) {
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my_ipi := Bool(false)
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}
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cpu.ipi_rep.valid := my_ipi
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cpu.ipi_req.ready := Bool(true)
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for (j <- 0 until nCores) {
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when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UInt(i)) {
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my_ipi := Bool(true)
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}
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}
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when (cpu.csr.req.fire()) { state := state_csr_resp }
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when (state === state_csr_req && me && csr_addr === UInt(csr_RESET)) {
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