depend on external cde library
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02d113b39f
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@ -2,6 +2,7 @@
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package uncore
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import Chisel._
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import cde.{Parameters, Field}
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abstract class StoreGen(typ: UInt, addr: UInt, dat: UInt) {
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val byte = typ === MT_B || typ === MT_BU
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@ -2,6 +2,7 @@
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package uncore
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import Chisel._
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import cde.{Parameters, Field}
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case object L2StoreDataQueueDepth extends Field[Int]
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@ -4,6 +4,7 @@ package uncore
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import Chisel._
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import scala.reflect.ClassTag
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import junctions._
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import cde.{Parameters, Field}
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case object CacheName extends Field[String]
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case object NSets extends Field[Int]
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@ -436,7 +437,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends
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val s_idle :: s_meta_read :: s_meta_resp :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 5)
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val state = Reg(init=s_idle)
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val xact = Reg(Bundle(new BufferedReleaseFromSrc()(p.alterPartial({case TLId => p(InnerTLId)}))))
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val xact = Reg(new BufferedReleaseFromSrc()(p.alterPartial({case TLId => p(InnerTLId)})))
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val xact_way_en = Reg{ Bits(width = nWays) }
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val xact_old_meta = Reg{ new L2Metadata }
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val coh = xact_old_meta.coh
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@ -530,7 +531,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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val state = Reg(init=s_idle)
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// State holding transaction metadata
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val xact = Reg(Bundle(new BufferedAcquireFromSrc()(p.alterPartial({ case TLId => p(InnerTLId) }))))
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val xact = Reg(new BufferedAcquireFromSrc()(p.alterPartial({ case TLId => p(InnerTLId) })))
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val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8)))
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val xact_tag_match = Reg{ Bool() }
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val xact_way_en = Reg{ Bits(width = nWays) }
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@ -5,6 +5,7 @@ package uncore
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import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import cde.{Parameters, Field}
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case object HtifKey extends Field[HtifParameters]
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@ -2,6 +2,7 @@
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package uncore
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import Chisel._
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import cde.{Parameters, Field}
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/** Base class to represent coherence information in clients and managers */
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abstract class CoherenceMetadata(implicit p: Parameters) extends TLBundle()(p) {
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@ -44,16 +45,15 @@ class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param op_code a memory operation from [[uncore.constants.MemoryOpConstants]]
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*/
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def makeAcquire(
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op_code: UInt,
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client_xact_id: UInt,
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addr_block: UInt): Acquire = {
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Bundle(Acquire(
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is_builtin_type = Bool(false),
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a_type = co.getAcquireType(op_code, this),
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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union = Cat(op_code, Bool(true)))(p))
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}
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op_code: UInt,
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client_xact_id: UInt,
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addr_block: UInt): Acquire =
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Acquire(
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is_builtin_type = Bool(false),
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a_type = co.getAcquireType(op_code, this),
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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union = Cat(op_code, Bool(true)))(p)
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/** Constructs a Release message based on this metadata on cache control op
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*
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@ -63,19 +63,18 @@ class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param data data being written back
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*/
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def makeVoluntaryRelease(
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op_code: UInt,
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Release = {
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Bundle(Release(
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op_code: UInt,
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Release =
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Release(
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voluntary = Bool(true),
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r_type = co.getReleaseType(op_code, this),
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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addr_beat = addr_beat,
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data = data)(p))
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}
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data = data)(p)
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/** Constructs a Release message based on this metadata on an eviction
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*
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@ -85,10 +84,10 @@ class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param data data being written back
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*/
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def makeVoluntaryWriteback(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Release =
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Release =
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makeVoluntaryRelease(
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op_code = M_FLUSH,
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client_xact_id = client_xact_id,
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@ -103,17 +102,16 @@ class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param data data being released
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*/
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def makeRelease(
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prb: Probe,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Release = {
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Bundle(Release(
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prb: Probe,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Release =
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Release(
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voluntary = Bool(false),
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r_type = co.getReleaseType(prb, this),
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client_xact_id = UInt(0),
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addr_block = prb.addr_block,
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addr_beat = addr_beat,
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data = data)(p))
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}
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data = data)(p)
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/** New metadata after receiving a [[uncore.Grant]]
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*
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@ -189,7 +187,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param acq Acquire message triggering this Probe
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*/
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def makeProbe(dst: UInt, acq: AcquireMetadata): ProbeToDst =
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Bundle(Probe(dst, co.getProbeType(acq, this), acq.addr_block)(p))
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Probe(dst, co.getProbeType(acq, this), acq.addr_block)(p)
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/** Construct an appropriate [[uncore.ProbeToDst]] for a given mem op
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*
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@ -198,7 +196,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param addr_block address of the cache block being probed
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*/
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def makeProbe(dst: UInt, op_code: UInt, addr_block: UInt): ProbeToDst =
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Bundle(Probe(dst, co.getProbeType(op_code, this), addr_block)(p))
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Probe(dst, co.getProbeType(op_code, this), addr_block)(p)
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/** Construct an appropriate [[uncore.ProbeToDst]] for an eviction
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*
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@ -213,14 +211,13 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param rel Release message being acknowledged by this Grant
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* @param manager_xact_id manager's transaction id
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*/
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def makeGrant(rel: ReleaseMetadata with HasClientId, manager_xact_id: UInt): GrantToDst = {
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Bundle(Grant(
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def makeGrant(rel: ReleaseMetadata with HasClientId, manager_xact_id: UInt): GrantToDst =
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Grant(
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dst = rel.client_id,
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is_builtin_type = Bool(true),
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g_type = Grant.voluntaryAckType,
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client_xact_id = rel.client_xact_id,
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manager_xact_id = manager_xact_id)(p))
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}
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manager_xact_id = manager_xact_id)(p)
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/** Construct an appropriate [[uncore.GrantToDst]] to respond to an [[uncore.Acquire]]
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*
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@ -232,11 +229,11 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param data data being refilled to the original requestor
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*/
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def makeGrant(
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acq: AcquireMetadata with HasClientId,
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manager_xact_id: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): GrantToDst = {
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Bundle(Grant(
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acq: AcquireMetadata with HasClientId,
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manager_xact_id: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): GrantToDst =
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Grant(
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dst = acq.client_id,
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is_builtin_type = acq.isBuiltInType(),
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g_type = Mux(acq.isBuiltInType(),
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@ -245,8 +242,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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client_xact_id = acq.client_xact_id,
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manager_xact_id = manager_xact_id,
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addr_beat = addr_beat,
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data = data)(p))
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}
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data = data)(p)
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/** Construct an [[uncore.GrantToDst]] to respond to an [[uncore.Acquire]] with some overrides
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*
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@ -259,10 +255,10 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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* @param data data being refilled to the original requestor
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*/
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def makeGrant(
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pri: AcquireMetadata with HasClientId,
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sec: SecondaryMissInfo,
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manager_xact_id: UInt,
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data: UInt): GrantToDst = {
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pri: AcquireMetadata with HasClientId,
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sec: SecondaryMissInfo,
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manager_xact_id: UInt,
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data: UInt): GrantToDst = {
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val g = makeGrant(pri, manager_xact_id, sec.addr_beat, data)
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g.client_xact_id := sec.client_xact_id
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g
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@ -309,8 +305,8 @@ object ManagerMetadata {
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* [[uncore.InnerTLId]] or [[uncore.OuterTLId]].
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*/
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class HierarchicalMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
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val inner: ManagerMetadata = Bundle(new ManagerMetadata()(p.alterPartial({case TLId => p(InnerTLId)})))
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val outer: ClientMetadata = Bundle(new ClientMetadata()(p.alterPartial({case TLId => p(OuterTLId)})))
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val inner: ManagerMetadata = new ManagerMetadata()(p.alterPartial({case TLId => p(InnerTLId)}))
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val outer: ClientMetadata = new ClientMetadata()(p.alterPartial({case TLId => p(OuterTLId)}))
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def ===(rhs: HierarchicalMetadata): Bool =
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this.inner === rhs.inner && this.outer === rhs.outer
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def !=(rhs: HierarchicalMetadata): Bool = !this.===(rhs)
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@ -2,6 +2,7 @@
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package uncore
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import Chisel._
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import cde.{Parameters, Field}
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case object LNEndpoints extends Field[Int]
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case object LNHeaderBits extends Field[Int]
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@ -2,6 +2,7 @@ package uncore
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import Chisel._
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import junctions._
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import cde.{Parameters, Field}
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case object RTCPeriod extends Field[Int]
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@ -2,6 +2,7 @@ package uncore
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import Chisel._
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import junctions.{SMIIO, MMIOBase}
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import cde.Parameters
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class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
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val rdata = Vec(Bits(INPUT, scrDataBits), nSCR)
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@ -4,6 +4,7 @@ package uncore
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import Chisel._
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import junctions._
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import scala.math.max
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import cde.{Parameters, Field}
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case object TLId extends Field[String]
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case class TLKey(id: String) extends Field[TileLinkParameters]
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@ -659,7 +660,7 @@ class GrantMetadata(implicit p: Parameters) extends ManagerToClientChannel()(p)
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def isVoluntary(dummy: Int = 0): Bool = isBuiltInType() && (g_type === Grant.voluntaryAckType)
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def requiresAck(dummy: Int = 0): Bool = !Bool(tlNetworkPreservesPointToPointOrdering) && !isVoluntary()
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def makeFinish(dummy: Int = 0): Finish = {
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val f = Wire(Bundle(new Finish))
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val f = Wire(new Finish)
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f.manager_xact_id := this.manager_xact_id
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f
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}
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package uncore
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import Chisel._
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import cde.{Parameters, Field}
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case object NReleaseTransactors extends Field[Int]
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case object NProbeTransactors extends Field[Int]
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@ -60,7 +61,7 @@ trait HasCoherenceAgentWiringHelpers {
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}
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trait HasInnerTLIO extends HasCoherenceAgentParameters {
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val inner = Bundle(new ManagerTileLinkIO()(p.alterPartial({case TLId => p(InnerTLId)})))
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val inner = new ManagerTileLinkIO()(p.alterPartial({case TLId => p(InnerTLId)}))
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val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput
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def iacq(dummy: Int = 0) = inner.acquire.bits
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def iprb(dummy: Int = 0) = inner.probe.bits
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@ -70,13 +71,13 @@ trait HasInnerTLIO extends HasCoherenceAgentParameters {
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}
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trait HasUncachedOuterTLIO extends HasCoherenceAgentParameters {
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val outer = Bundle(new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)})))
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val outer = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)}))
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def oacq(dummy: Int = 0) = outer.acquire.bits
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def ognt(dummy: Int = 0) = outer.grant.bits
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}
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trait HasCachedOuterTLIO extends HasCoherenceAgentParameters {
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val outer = Bundle(new ClientTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)})))
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val outer = new ClientTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)}))
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def oacq(dummy: Int = 0) = outer.acquire.bits
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def oprb(dummy: Int = 0) = outer.probe.bits
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def orel(dummy: Int = 0) = outer.release.bits
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