riscv/rocket-chip
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Fix HTIF for cache line sizes other than 64 B

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Andrew Waterman
2014-01-22 18:20:36 -08:00
parent 4f1213cb8b
commit 3e634aef1d
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/htif.scala
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@@ -56,7 +56,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int)(implicit conf: TileLinkConfigurati
// system is 'interesting' if any tile is 'interesting'
val short_request_bits = 64
val long_request_bits = 576
val long_request_bits = short_request_bits + MEM_DATA_BITS*REFILL_CYCLES
require(short_request_bits % w == 0)
val rx_count_w = 13 + log2Up(64) - log2Up(w) // data size field is 12 bits