riscv/rocket-chip
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GlobalAddrMap

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This commit is contained in:
Henry Cook 2015-10-06 18:19:45 -07:00
parent 31be6407ec
commit 66ea39638e
2 changed files with 3 additions and 3 deletions
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3
uncore/src/main/scala/cache.scala
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@ -11,7 +11,6 @@ case object NWays extends Field[Int]
case object RowBits extends Field[Int]
case object Replacer extends Field[() => ReplacementPolicy]
case object AmoAluOperandBits extends Field[Int]
case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
case object NPrimaryMisses extends Field[Int]
case object NSecondaryMisses extends Field[Int]
case object CacheBlockBytes extends Field[Int]
@ -169,6 +168,8 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
io.write.ready := !rst
}
case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
trait HasL2HellaCacheParameters extends HasCacheParameters with HasCoherenceAgentParameters {
val idxMSB = idxBits-1
val idxLSB = 0

3
uncore/src/main/scala/rtc.scala
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@ -8,8 +8,7 @@ case object RTCPeriod extends Field[Int]
class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule {
val io = new NastiIO
private val addrMap = new AddrHashMap(p(NastiAddrMap))
val addrMap = new AddrHashMap(p(GlobalAddrMap))
val addrTable = Vec.tabulate(nCores) { i =>
UInt(addrMap(s"conf:csr$i").start + csr_MTIME * scrDataBytes)
}