Finish adding TLDataBeats to uncore & hub
This commit is contained in:
Henry Cook
parent
2f733a60db
commit
3026c46a9c
@ -30,7 +30,8 @@ abstract trait CacheParameters extends UsesParameters {
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val rowWords = rowBits/wordBits
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val rowBytes = rowBits/8
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val rowOffBits = log2Up(rowBytes)
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val refillCycles = params(TLDataBits)/rowBits
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val refillCyclesPerBeat = params(TLDataBits)/rowBits
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val refillCycles = refillCyclesPerBeat*params(TLDataBeats)
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}
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abstract class CacheBundle extends Bundle with CacheParameters
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@ -99,7 +100,6 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
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abstract trait L2HellaCacheParameters extends CacheParameters
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with CoherenceAgentParameters
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with TileLinkParameters
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters
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@ -3,12 +3,6 @@
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package uncore
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import Chisel._
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object MuxBundle {
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def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
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mapping.reverse.foldLeft(default)((b, a) => Mux(a._1, a._2, b))
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}
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}
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abstract class CoherenceMetadata extends Bundle
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object ClientMetadata {
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@ -13,6 +13,7 @@ case object HTIFNCores extends Field[Int]
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abstract trait HTIFParameters extends UsesParameters {
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val dataBits = params(TLDataBits)
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val dataBeats = params(TLDataBeats)
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val co = params(TLCoherence)
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val w = params(HTIFWidth)
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val nSCR = params(HTIFNSCR)
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@ -71,7 +72,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
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// system is 'interesting' if any tile is 'interesting'
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val short_request_bits = 64
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val long_request_bits = short_request_bits + dataBits
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val long_request_bits = short_request_bits + dataBits*dataBeats
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require(short_request_bits % w == 0)
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val rx_count_w = 13 + log2Up(64) - log2Up(w) // data size field is 12 bits
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@ -150,12 +151,13 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
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state_tx)))
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}
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val acq_q = Module(new Queue(new Acquire, 1))
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when (state === state_mem_wreq && acq_q.io.enq.ready) {
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state := state_mem_wresp
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val (cnt, cnt_done) = Counter((state === state_mem_wreq && io.mem.acquire.ready) ||
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(state === state_mem_rresp && io.mem.grant.valid), dataBeats)
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when (state === state_mem_wreq) {
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when (cnt_done) { state := state_mem_wresp }
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}
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when (state === state_mem_rreq && acq_q.io.enq.ready) {
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state := state_mem_rresp
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when (state === state_mem_rreq) {
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when(io.mem.acquire.ready) { state := state_mem_rresp }
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}
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when (state === state_mem_wresp) {
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when (mem_acked) {
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@ -164,10 +166,10 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
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}
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}
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when (state === state_mem_rresp) {
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when (io.mem.grant.valid) {
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when (cnt_done) {
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state := state_mem_finish
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mem_acked := Bool(false)
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}
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mem_acked := Bool(false)
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}
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when (state === state_mem_finish && io.mem.finish.ready) {
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state := Mux(cmd === cmd_readmem || pos === UInt(1), state_tx, state_rx)
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@ -182,22 +184,19 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
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state := Mux(cmd === cmd_readmem && pos != UInt(0), state_mem_rreq, state_rx)
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}
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var mem_req_data: Bits = null
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var mem_req_data: UInt = null
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for (i <- 0 until dataBits/short_request_bits) {
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val idx = UInt(i, log2Up(dataBits/short_request_bits))
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val idx = Cat(cnt, UInt(i, log2Up(dataBits/short_request_bits)))
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when (state === state_mem_rresp && io.mem.grant.valid) {
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packet_ram(idx) := io.mem.grant.bits.payload.data((i+1)*short_request_bits-1, i*short_request_bits)
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}
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mem_req_data = Cat(packet_ram(idx), mem_req_data)
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}
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acq_q.io.enq.valid := state === state_mem_rreq || state === state_mem_wreq
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val init_addr = addr.toUInt >> UInt(offsetBits-3)
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acq_q.io.enq.bits := Mux(cmd === cmd_writemem,
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UncachedWrite(init_addr, UInt(0)),
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io.mem.acquire.valid := state === state_mem_rreq || state === state_mem_wreq
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io.mem.acquire.bits.payload := Mux(cmd === cmd_writemem,
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UncachedWrite(init_addr, mem_req_data),
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UncachedRead(init_addr))
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io.mem.acquire.valid := acq_q.io.deq.valid
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acq_q.io.deq.ready := io.mem.acquire.ready
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io.mem.acquire.bits.payload := acq_q.io.deq.bits
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io.mem.acquire.bits.payload.data := mem_req_data
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io.mem.acquire.bits.header.src := UInt(params(LNClients)) // By convention HTIF is the client with the largest id
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io.mem.acquire.bits.header.dst := UInt(0) // DNC; Overwritten outside module
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@ -255,7 +254,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
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for (i <- 0 until scr_rdata.size)
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scr_rdata(i) := io.scr.rdata(i)
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scr_rdata(0) := UInt(nCores)
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scr_rdata(1) := UInt((BigInt(dataBits/8) << acq_q.io.enq.bits.addr.getWidth) >> 20)
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scr_rdata(1) := UInt((BigInt(dataBits*dataBeats/8) << params(TLAddrBits)) >> 20)
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io.scr.wen := Bool(false)
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io.scr.wdata := pcr_wdata
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@ -209,81 +209,122 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int) extends Module {
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val mem = new MemIO
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}
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val co = params(TLCoherence)
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val tbits = params(MIFTagBits)
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val dbits = params(MIFDataBits)
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val dbeats = params(MIFDataBeats)
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require(params(TLDataBits) == dbits*dbeats)
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val mifTagBits = params(MIFTagBits)
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val mifDataBits = params(MIFDataBits)
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val mifDataBeats = params(MIFDataBeats)
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val tlDataBits = params(TLDataBits)
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val tlDataBeats = params(TLDataBeats)
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val dataBits = tlDataBits*tlDataBeats
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require(tlDataBits*tlDataBeats == mifDataBits*mifDataBeats)
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//require(params(TLClientXactIdBits) <= params(MIFTagBits))
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// Decompose outgoing TL Acquires into MemIO cmd and data
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val mem_cmd_q = Module(new Queue(new MemReqCmd, qDepth))
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val mem_data_q = Module(new Queue(new MemData, qDepth))
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val cnt_max = dbeats
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val cnt_out = Reg(UInt(width = log2Up(cnt_max+1)))
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io.uncached.acquire.ready := Bool(false)
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io.uncached.grant.valid := Bool(false)
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io.mem.resp.ready := Bool(false)
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mem_cmd_q.io.enq.valid := Bool(false)
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mem_data_q.io.enq.valid := Bool(false)
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val acq_has_data = co.messageHasData(io.uncached.acquire.bits.payload)
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val (tl_cnt_out, tl_wrap_out) = Counter(io.uncached.acquire.fire() && acq_has_data, tlDataBeats)
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val (mif_cnt_out, mif_wrap_out) = Counter(mem_data_q.io.enq.fire(), mifDataBeats)
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val active_out = Reg(init=Bool(false))
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val cmd_sent_out = Reg(init=Bool(false))
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val buf_out = Reg(Bits())
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val tl_done_out = Reg(init=Bool(false))
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val mif_done_out = Reg(init=Bool(false))
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val tag_out = Reg(Bits())
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val addr_out = Reg(Bits())
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val has_data = Reg(init=Bool(false))
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val tl_buf_out = Vec.fill(tlDataBeats){ Reg(io.uncached.acquire.bits.payload.data.clone) }
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val mif_buf_out = Vec.fill(mifDataBeats){ new MemData }
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mif_buf_out := mif_buf_out.fromBits(tl_buf_out.toBits)
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val mif_prog_out = (mif_cnt_out+UInt(1, width = log2Up(mifDataBeats+1)))*UInt(mifDataBits)
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val tl_prog_out = tl_cnt_out*UInt(tlDataBits)
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val cnt_in = Reg(UInt(width = log2Up(cnt_max+1)))
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val active_in = Reg(init=Bool(false))
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val buf_in = Reg(Bits())
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val tag_in = Reg(UInt(width = tbits))
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// Decompose outgoing TL Acquires into MemIO cmd and data
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when(!active_out && io.uncached.acquire.valid) {
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active_out := Bool(true)
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cmd_sent_out := Bool(false)
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cnt_out := UInt(0)
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buf_out := io.uncached.acquire.bits.payload.data
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tag_out := io.uncached.acquire.bits.payload.client_xact_id
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addr_out := io.uncached.acquire.bits.payload.addr
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has_data := co.messageHasData(io.uncached.acquire.bits.payload)
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when(!active_out){
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io.uncached.acquire.ready := Bool(true)
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when(io.uncached.acquire.valid) {
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active_out := Bool(true)
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cmd_sent_out := Bool(false)
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tag_out := io.uncached.acquire.bits.payload.client_xact_id
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addr_out := io.uncached.acquire.bits.payload.addr
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has_data := acq_has_data
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tl_done_out := tl_wrap_out
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mif_done_out := Bool(false)
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tl_buf_out(tl_cnt_out) := io.uncached.acquire.bits.payload.data
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}
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}
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when(active_out) {
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when(!cmd_sent_out) {
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mem_cmd_q.io.enq.valid := Bool(true)
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}
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when(has_data) {
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when(!tl_done_out) {
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io.uncached.acquire.ready := Bool(true)
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when(io.uncached.acquire.valid) {
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tl_buf_out(tl_cnt_out) := io.uncached.acquire.bits.payload.data
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}
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}
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when(!mif_done_out) {
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mem_data_q.io.enq.valid := tl_done_out || mif_prog_out <= tl_prog_out
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}
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}
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when(mem_cmd_q.io.enq.fire()) {
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cmd_sent_out := Bool(true)
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}
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when(mem_data_q.io.enq.fire()) {
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cnt_out := cnt_out + UInt(1)
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buf_out := buf_out >> UInt(dbits)
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}
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when(cmd_sent_out && (!has_data || cnt_out === UInt(cnt_max))) {
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when(tl_wrap_out) { tl_done_out := Bool(true) }
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when(mif_wrap_out) { mif_done_out := Bool(true) }
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when(cmd_sent_out && (!has_data || mif_done_out)) {
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active_out := Bool(false)
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}
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}
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io.uncached.acquire.ready := !active_out
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mem_cmd_q.io.enq.valid := active_out && !cmd_sent_out
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mem_cmd_q.io.enq.bits.rw := has_data
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mem_cmd_q.io.enq.bits.tag := tag_out
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mem_cmd_q.io.enq.bits.addr := addr_out
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mem_data_q.io.enq.valid := active_out && has_data && cnt_out < UInt(cnt_max)
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mem_data_q.io.enq.bits.data := buf_out
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mem_data_q.io.enq.bits.data := mif_buf_out(mif_cnt_out).data
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io.mem.req_cmd <> mem_cmd_q.io.deq
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io.mem.req_data <> mem_data_q.io.deq
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// Aggregate incoming MemIO responses into TL Grants
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io.mem.resp.ready := !active_in || cnt_in < UInt(cnt_max)
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io.uncached.grant.valid := active_in && (cnt_in === UInt(cnt_max))
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io.uncached.grant.bits.payload := Grant(Bool(true), Grant.uncachedRead, tag_in, UInt(0), buf_in)
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when(!active_in && io.mem.resp.valid) {
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active_in := Bool(true)
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cnt_in := UInt(1)
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buf_in := io.mem.resp.bits.data << UInt(dbits*(cnt_max-1))
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tag_in := io.mem.resp.bits.tag
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val (mif_cnt_in, mif_wrap_in) = Counter(io.mem.resp.fire(), mifDataBeats) // TODO: Assumes all resps have data
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val (tl_cnt_in, tl_wrap_in) = Counter(io.uncached.grant.fire(), tlDataBeats)
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val active_in = Reg(init=Bool(false))
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val mif_done_in = Reg(init=Bool(false))
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val tag_in = Reg(UInt(width = mifTagBits))
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val mif_buf_in = Vec.fill(mifDataBeats){ Reg(new MemData) }
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val tl_buf_in = Vec.fill(tlDataBeats){ io.uncached.acquire.bits.payload.data.clone }
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tl_buf_in := tl_buf_in.fromBits(mif_buf_in.toBits)
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val tl_prog_in = (tl_cnt_in+UInt(1, width = log2Up(tlDataBeats+1)))*UInt(tlDataBits)
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val mif_prog_in = mif_cnt_in*UInt(mifDataBits)
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when(!active_in) {
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io.mem.resp.ready := Bool(true)
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when(io.mem.resp.valid) {
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active_in := Bool(true)
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mif_done_in := mif_wrap_in
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tag_in := io.mem.resp.bits.tag
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mif_buf_in(tl_cnt_in).data := io.mem.resp.bits.data
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}
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}
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when(active_in) {
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when(io.uncached.grant.fire()) {
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active_in := Bool(false)
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}
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when(io.mem.resp.fire()) {
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buf_in := Cat(io.mem.resp.bits.data, buf_in(cnt_max*dbits-1,dbits))
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cnt_in := cnt_in + UInt(1)
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io.uncached.grant.valid := mif_done_in || tl_prog_in <= mif_prog_in
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when(!mif_done_in) {
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io.mem.resp.ready := Bool(true)
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when(io.mem.resp.valid) {
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mif_buf_in(mif_cnt_in).data := io.mem.resp.bits.data
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}
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}
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when(mif_wrap_in) { mif_done_in := Bool(true) }
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when(tl_wrap_in) { active_in := Bool(false) }
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}
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io.uncached.grant.bits.payload := Grant(Bool(true), Grant.uncachedRead, tag_in, UInt(0),
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tl_buf_in(tl_cnt_in))
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}
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class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module
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@ -390,8 +431,8 @@ class MemPipeIOUncachedTileLinkIOConverter(outstanding: Int, refillCycles: Int)
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val a = Module(new MemIOUncachedTileLinkIOConverter(2))
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val b = Module(new MemPipeIOMemIOConverter(outstanding, refillCycles))
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a.io.uncached <> io.uncached
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b.io.cpu.req_cmd <> Queue(a.io.mem.req_cmd, 2)
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b.io.cpu.req_data <> Queue(a.io.mem.req_data, refillCycles)
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b.io.cpu.req_cmd <> Queue(a.io.mem.req_cmd, 2, pipe=true)
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b.io.cpu.req_data <> Queue(a.io.mem.req_data, refillCycles, pipe=true)
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a.io.mem.resp <> b.io.cpu.resp
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b.io.mem <> io.mem
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}
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@ -26,9 +26,11 @@ abstract trait TileLinkParameters extends UsesParameters {
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(tlSubblockAddrBits +
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tlUncachedOperandSizeBits +
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tlAtomicOpcodeBits))
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val co = params(TLCoherence)
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}
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class TLBundle extends Bundle with TileLinkParameters
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abstract class TLBundle extends Bundle with TileLinkParameters
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abstract class TLModule extends Module with TileLinkParameters
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trait HasPhysicalAddress extends TLBundle {
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val addr = UInt(width = tlAddrBits)
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@ -55,7 +57,7 @@ class Acquire extends ClientSourcedMessage
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with HasClientTransactionId
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with HasTileLinkData {
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val uncached = Bool()
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val a_type = UInt(width = max(log2Up(Acquire.nUncachedAcquireTypes), params(TLCoherence).acquireTypeWidth))
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val a_type = UInt(width = max(log2Up(Acquire.nUncachedAcquireTypes), co.acquireTypeWidth))
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val subblock = Bits(width = tlSubblockUnionBits)
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val sbAddrOff = tlSubblockAddrBits + tlUncachedOperandSizeBits
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val opSzOff = tlUncachedOperandSizeBits + sbAddrOff
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@ -147,7 +149,7 @@ object Probe {
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class Probe extends MasterSourcedMessage
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with HasPhysicalAddress {
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val p_type = UInt(width = params(TLCoherence).probeTypeWidth)
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val p_type = UInt(width = co.probeTypeWidth)
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def is(t: UInt) = p_type === t
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}
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@ -172,7 +174,7 @@ class Release extends ClientSourcedMessage
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with HasPhysicalAddress
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with HasClientTransactionId
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with HasTileLinkData {
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val r_type = UInt(width = params(TLCoherence).releaseTypeWidth)
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val r_type = UInt(width = co.releaseTypeWidth)
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def is(t: UInt) = r_type === t
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}
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@ -181,7 +183,7 @@ class Grant extends MasterSourcedMessage
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with HasClientTransactionId
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with HasMasterTransactionId {
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val uncached = Bool()
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val g_type = UInt(width = max(log2Up(Grant.nUncachedGrantTypes), params(TLCoherence).grantTypeWidth))
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val g_type = UInt(width = max(log2Up(Grant.nUncachedGrantTypes), co.grantTypeWidth))
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def is(t: UInt) = g_type === t
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}
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@ -221,7 +223,7 @@ class TileLinkIO extends UncachedTileLinkIO {
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val release = new DecoupledIO(new LogicalNetworkIO(new Release))
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}
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abstract class TileLinkArbiterLike(val arbN: Int) extends Module {
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abstract class TileLinkArbiterLike(val arbN: Int) extends TLModule {
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type MasterSourcedWithId = MasterSourcedMessage with HasClientTransactionId
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type ClientSourcedWithId = ClientSourcedMessage with HasClientTransactionId
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@ -232,8 +234,8 @@ abstract class TileLinkArbiterLike(val arbN: Int) extends Module {
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def hookupClientSource[M <: ClientSourcedWithId]
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(ins: Seq[DecoupledIO[LogicalNetworkIO[M]]],
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out: DecoupledIO[LogicalNetworkIO[M]]) {
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def hasData(m: LogicalNetworkIO[M]) = params(TLCoherence).messageHasData(m.payload)
|
||||
val arb = Module(new RRArbiter(out.bits.clone, arbN))
|
||||
def hasData(m: LogicalNetworkIO[M]) = co.messageHasData(m.payload)
|
||||
val arb = Module(new LockingRRArbiter(out.bits.clone, arbN, params(TLDataBeats), Some(hasData _)))
|
||||
out <> arb.io.out
|
||||
ins.zipWithIndex.zip(arb.io.in).map{ case ((req,id), arb) => {
|
||||
arb.valid := req.valid
|
||||
|
||||
@ -8,14 +8,16 @@ case object NAcquireTransactors extends Field[Int]
|
||||
case object L2StoreDataQueueDepth extends Field[Int]
|
||||
case object NClients extends Field[Int]
|
||||
|
||||
abstract trait CoherenceAgentParameters extends UsesParameters {
|
||||
val co = params(TLCoherence)
|
||||
abstract trait CoherenceAgentParameters extends UsesParameters
|
||||
with TileLinkParameters {
|
||||
val nReleaseTransactors = 1
|
||||
val nAcquireTransactors = params(NAcquireTransactors)
|
||||
val nTransactors = nReleaseTransactors + nAcquireTransactors
|
||||
val nClients = params(NClients)
|
||||
val sdqDepth = params(L2StoreDataQueueDepth)
|
||||
val sdqIdBits = math.max(log2Up(nReleaseTransactors) + 1, log2Up(params(L2StoreDataQueueDepth))) + 1
|
||||
val sdqDepth = params(L2StoreDataQueueDepth)*tlDataBeats
|
||||
val dqIdxBits = math.max(log2Up(nReleaseTransactors) + 1, log2Up(params(L2StoreDataQueueDepth))) +
|
||||
log2Ceil(tlDataBeats)
|
||||
val nDataQueueLocations = 3 //Stores, VoluntaryWBs, Releases
|
||||
}
|
||||
|
||||
abstract class CoherenceAgent(innerId: String, outerId: String) extends Module
|
||||
@ -27,75 +29,93 @@ abstract class CoherenceAgent(innerId: String, outerId: String) extends Module
|
||||
}
|
||||
}
|
||||
|
||||
class DataQueueLocation extends Bundle with CoherenceAgentParameters {
|
||||
val idx = UInt(width = dqIdxBits)
|
||||
val loc = UInt(width = log2Ceil(nDataQueueLocations))
|
||||
}
|
||||
object DataQueueLocation {
|
||||
def apply(idx: UInt, loc: UInt) = {
|
||||
val d = new DataQueueLocation
|
||||
d.idx := idx
|
||||
d.loc := loc
|
||||
d
|
||||
}
|
||||
}
|
||||
|
||||
class L2CoherenceAgent(bankId: Int, innerId: String, outerId: String) extends
|
||||
CoherenceAgent(innerId, outerId) {
|
||||
|
||||
// Queue to store impending UncachedWrite data
|
||||
val sdq_val = Reg(init=Bits(0, sdqDepth))
|
||||
val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
|
||||
val sdq_rdy = !sdq_val.andR
|
||||
val sdq_enq = io.inner.acquire.valid && io.inner.acquire.ready && co.messageHasData(io.inner.acquire.bits.payload)
|
||||
val sdq = Vec.fill(sdqDepth){Reg(io.inner.acquire.bits.payload.data)}
|
||||
when (sdq_enq) { sdq(sdq_alloc_id) := io.inner.acquire.bits.payload.data }
|
||||
val internalDataBits = new DataQueueLocation().getWidth
|
||||
val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
|
||||
|
||||
// Create SHRs for outstanding transactions
|
||||
val trackerList = (0 until nReleaseTransactors).map(id =>
|
||||
Module(new VoluntaryReleaseTracker(id, bankId, innerId, outerId), {case TLDataBits => sdqIdBits})) ++
|
||||
Module(new VoluntaryReleaseTracker(id, bankId, innerId, outerId), {case TLDataBits => internalDataBits})) ++
|
||||
(nReleaseTransactors until nTransactors).map(id =>
|
||||
Module(new AcquireTracker(id, bankId, innerId, outerId), {case TLDataBits => sdqIdBits}))
|
||||
Module(new AcquireTracker(id, bankId, innerId, outerId), {case TLDataBits => internalDataBits}))
|
||||
|
||||
// Propagate incoherence flags
|
||||
trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
|
||||
|
||||
// Handle acquire transaction initiation
|
||||
// Queue to store impending UncachedWrite data
|
||||
val acquire = io.inner.acquire
|
||||
val sdq_val = Reg(init=Bits(0, sdqDepth))
|
||||
val sdq_alloc_id = PriorityEncoder(~sdq_val)
|
||||
val sdq_rdy = !sdq_val.andR
|
||||
val sdq_enq = acquire.fire() && co.messageHasData(acquire.bits.payload)
|
||||
val sdq = Vec.fill(sdqDepth){ Reg(io.inner.acquire.bits.payload.data) }
|
||||
when (sdq_enq) { sdq(sdq_alloc_id) := acquire.bits.payload.data }
|
||||
|
||||
// Handle acquire transaction initiation
|
||||
val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
|
||||
val block_acquires = any_acquire_conflict
|
||||
|
||||
val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
|
||||
for( i <- 0 until trackerList.size ) {
|
||||
val t = trackerList(i).io.inner
|
||||
alloc_arb.io.in(i).valid := t.acquire.ready
|
||||
t.acquire.bits := acquire.bits
|
||||
t.acquire.bits.payload.data := Cat(sdq_alloc_id, UInt(1))
|
||||
t.acquire.bits.payload.data := DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
|
||||
t.acquire.valid := alloc_arb.io.in(i).ready
|
||||
}
|
||||
acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && sdq_rdy && !block_acquires
|
||||
alloc_arb.io.out.ready := acquire.valid && sdq_rdy && !block_acquires
|
||||
|
||||
// Handle probe request generation
|
||||
val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
|
||||
io.inner.probe <> probe_arb.io.out
|
||||
probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.probe }
|
||||
|
||||
// Handle releases, which might be voluntary and might have data
|
||||
// Queue to store impending Voluntary Release data
|
||||
val release = io.inner.release
|
||||
val voluntary = co.isVoluntary(release.bits.payload)
|
||||
val vwbdq_enq = release.fire() && voluntary && co.messageHasData(release.bits.payload)
|
||||
val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, tlDataBeats) //TODO Zero width
|
||||
val vwbdq = Vec.fill(tlDataBeats){ Reg(release.bits.payload.data) } //TODO Assumes nReleaseTransactors == 1
|
||||
when(vwbdq_enq) { vwbdq(rel_data_cnt) := release.bits.payload.data }
|
||||
|
||||
// Handle releases, which might be voluntary and might have data
|
||||
val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
|
||||
val block_releases = Bool(false)
|
||||
val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
|
||||
val release_idx = Mux(voluntary, UInt(0), conflict_idx)
|
||||
// TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
|
||||
for( i <- 0 until trackerList.size ) {
|
||||
val t = trackerList(i).io.inner
|
||||
t.release.bits := release.bits
|
||||
t.release.bits.payload.data := (if (i < nReleaseTransactors) Cat(UInt(i), UInt(2)) else UInt(0))
|
||||
t.release.bits.payload.data := (if (i < nReleaseTransactors)
|
||||
DataQueueLocation(rel_data_cnt, inVolWBQueue)
|
||||
else DataQueueLocation(UInt(0), inClientReleaseQueue)).toBits
|
||||
t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
|
||||
}
|
||||
release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
|
||||
|
||||
val vwbdq = Vec.fill(nReleaseTransactors){ Reg(release.bits.payload.data) }
|
||||
when(voluntary && release.fire()) {
|
||||
vwbdq(release_idx) := release.bits.payload.data
|
||||
}
|
||||
// Wire probe requests to clients
|
||||
val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
|
||||
io.inner.probe <> probe_arb.io.out
|
||||
probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.probe }
|
||||
|
||||
// Reply to initial requestor
|
||||
val grant_arb = Module(new Arbiter(new LogicalNetworkIO(new Grant), trackerList.size))
|
||||
// Wire grant reply to initiating client
|
||||
def hasData(m: LogicalNetworkIO[Grant]) = co.messageHasData(m.payload)
|
||||
val grant_arb = Module(new LockingArbiter(new LogicalNetworkIO(new Grant), trackerList.size, tlDataBeats, Some(hasData _)))
|
||||
io.inner.grant.bits.payload.data := io.outer.grant.bits.payload.data
|
||||
io.inner.grant <> grant_arb.io.out
|
||||
grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.grant }
|
||||
|
||||
// Free finished transactions
|
||||
// Wire finished transaction acks
|
||||
val ack = io.inner.finish
|
||||
trackerList.map(_.io.inner.finish.valid := ack.valid)
|
||||
trackerList.map(_.io.inner.finish.bits := ack.bits)
|
||||
@ -103,27 +123,28 @@ class L2CoherenceAgent(bankId: Int, innerId: String, outerId: String) extends
|
||||
|
||||
// Create an arbiter for the one memory port
|
||||
val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size),
|
||||
{ case TLId => outerId; case TLDataBits => sdqIdBits })
|
||||
{ case TLId => outerId; case TLDataBits => internalDataBits })
|
||||
outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer }
|
||||
val is_in_sdq = outer_arb.io.out.acquire.bits.payload.data(0)
|
||||
val is_in_vwbdq = outer_arb.io.out.acquire.bits.payload.data(1)
|
||||
val free_sdq_id = outer_arb.io.out.acquire.bits.payload.data >> UInt(1)
|
||||
val free_vwbdq_id = outer_arb.io.out.acquire.bits.payload.data >> UInt(2)
|
||||
val free_sdq = io.outer.acquire.fire() && co.messageHasData(io.outer.acquire.bits.payload) && is_in_sdq
|
||||
io.outer.acquire.bits.payload.data := Mux(is_in_sdq, sdq(free_sdq_id),
|
||||
Mux(is_in_vwbdq, vwbdq(free_vwbdq_id), release.bits.payload.data))
|
||||
val outer_data_ptr = new DataQueueLocation().fromBits(outer_arb.io.out.acquire.bits.payload.data)
|
||||
val is_in_sdq = outer_data_ptr.loc === inStoreQueue
|
||||
val free_sdq = io.outer.acquire.fire() &&
|
||||
co.messageHasData(io.outer.acquire.bits.payload) &&
|
||||
outer_data_ptr.loc === inStoreQueue
|
||||
io.outer.acquire.bits.payload.data := MuxLookup(outer_data_ptr.loc, release.bits.payload.data, Array(
|
||||
inStoreQueue -> sdq(outer_data_ptr.idx),
|
||||
inVolWBQueue -> vwbdq(outer_data_ptr.idx)))
|
||||
io.outer <> outer_arb.io.out
|
||||
|
||||
// Update SDQ valid bits
|
||||
when (io.outer.acquire.valid || sdq_enq) {
|
||||
sdq_val := sdq_val & ~(UIntToOH(free_sdq_id) & Fill(sdqDepth, free_sdq)) |
|
||||
sdq_val := sdq_val & ~(UIntToOH(outer_data_ptr.idx) & Fill(sdqDepth, free_sdq)) |
|
||||
PriorityEncoderOH(~sdq_val(sdqDepth-1,0)) & Fill(sdqDepth, sdq_enq)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
abstract class XactTracker(innerId: String, outerId: String) extends Module {
|
||||
val (co, nClients) = (params(TLCoherence),params(NClients))
|
||||
val (co, nClients, tlDataBeats) = (params(TLCoherence),params(NClients),params(TLDataBeats))
|
||||
val io = new Bundle {
|
||||
val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
|
||||
val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
|
||||
@ -137,13 +158,20 @@ abstract class XactTracker(innerId: String, outerId: String) extends Module {
|
||||
val c_gnt = io.inner.grant.bits
|
||||
val c_ack = io.inner.finish.bits
|
||||
val m_gnt = io.outer.grant.bits
|
||||
|
||||
}
|
||||
|
||||
class VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends XactTracker(innerId, outerId) {
|
||||
val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
|
||||
val s_idle :: s_outer :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
|
||||
val state = Reg(init=s_idle)
|
||||
val xact = Reg{ new Release }
|
||||
val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
|
||||
val data_ptrs = Vec.fill(tlDataBeats){ Reg(io.inner.release.bits.payload.data.clone) }
|
||||
val collect_inner_data = Reg(init=Bool(false))
|
||||
val (inner_data_cnt, inner_data_done) =
|
||||
Counter(io.inner.release.fire() && co.messageHasData(io.inner.release.bits.payload), tlDataBeats)
|
||||
val (outer_data_cnt, outer_data_done) =
|
||||
Counter(io.outer.acquire.fire() && co.messageHasData(io.outer.acquire.bits.payload), tlDataBeats)
|
||||
|
||||
io.has_acquire_conflict := Bool(false)
|
||||
io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) &&
|
||||
@ -156,7 +184,7 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, oute
|
||||
io.outer.acquire.bits.payload := Bundle(UncachedWrite(
|
||||
xact.addr,
|
||||
UInt(trackerId),
|
||||
xact.data),
|
||||
data_ptrs(outer_data_cnt)),
|
||||
{ case TLId => outerId })
|
||||
io.inner.acquire.ready := Bool(false)
|
||||
io.inner.probe.valid := Bool(false)
|
||||
@ -169,18 +197,28 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, oute
|
||||
xact.client_xact_id,
|
||||
UInt(trackerId))
|
||||
|
||||
when(collect_inner_data) {
|
||||
io.inner.release.ready := Bool(true)
|
||||
when(io.inner.release.valid) {
|
||||
data_ptrs(inner_data_cnt) := c_rel.payload.data
|
||||
}
|
||||
when(inner_data_done) { collect_inner_data := Bool(false) }
|
||||
}
|
||||
|
||||
switch (state) {
|
||||
is(s_idle) {
|
||||
io.inner.release.ready := Bool(true)
|
||||
when( io.inner.release.valid ) {
|
||||
io.inner.release.ready := Bool(true)
|
||||
xact := c_rel.payload
|
||||
init_client_id := c_rel.header.src
|
||||
state := Mux(co.messageHasData(c_rel.payload), s_mem, s_ack)
|
||||
data_ptrs(UInt(0)) := c_rel.payload.data
|
||||
collect_inner_data := co.messageHasData(c_rel.payload)
|
||||
state := Mux(co.messageHasData(c_rel.payload), s_outer, s_ack)
|
||||
}
|
||||
}
|
||||
is(s_mem) {
|
||||
io.outer.acquire.valid := Bool(true)
|
||||
when(io.outer.acquire.ready) { state := s_ack }
|
||||
is(s_outer) {
|
||||
io.outer.acquire.valid := (if(tlDataBeats == 1) Bool(true) else !collect_inner_data || (outer_data_cnt < inner_data_cnt))
|
||||
when(outer_data_done) { state := s_ack }
|
||||
}
|
||||
is(s_ack) {
|
||||
io.inner.grant.valid := Bool(true)
|
||||
@ -195,6 +233,12 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
|
||||
val xact = Reg{ new Acquire }
|
||||
val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
|
||||
//TODO: Will need id reg for merged release xacts
|
||||
val data_ptrs = Vec.fill(tlDataBeats){ Reg(io.inner.acquire.bits.payload.data.clone) }
|
||||
val collect_inner_data = Reg(init=Bool(false))
|
||||
val (inner_data_cnt, inner_data_done) =
|
||||
Counter(io.inner.acquire.fire() && co.messageHasData(io.inner.acquire.bits.payload), tlDataBeats)
|
||||
val (outer_data_cnt, outer_data_done) =
|
||||
Counter(io.outer.acquire.fire() && co.messageHasData(io.outer.acquire.bits.payload), tlDataBeats)
|
||||
|
||||
val release_count = if (nClients == 1) UInt(0) else Reg(init=UInt(0, width = log2Up(nClients)))
|
||||
val probe_flags = Reg(init=Bits(0, width = nClients))
|
||||
@ -202,23 +246,21 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
|
||||
|
||||
val pending_outer_write = co.messageHasData(xact)
|
||||
val pending_outer_read = co.requiresOuterRead(xact, co.masterMetadataOnFlush)
|
||||
val outer_write_acq = Bundle(UncachedWrite(xact.addr, UInt(trackerId), xact.data),
|
||||
val outer_write_acq = Bundle(UncachedWrite(xact.addr, UInt(trackerId), data_ptrs(outer_data_cnt)),
|
||||
{ case TLId => outerId })
|
||||
val outer_write_rel = Bundle(UncachedWrite(xact.addr, UInt(trackerId), UInt(0)), // Special SQDId
|
||||
val outer_write_rel = Bundle(UncachedWrite(xact.addr, UInt(trackerId), c_rel.payload.data),
|
||||
{ case TLId => outerId })
|
||||
val outer_read = Bundle(UncachedRead(xact.addr, UInt(trackerId)),
|
||||
{ case TLId => outerId })
|
||||
|
||||
val probe_initial_flags = Bits(width = nClients)
|
||||
probe_initial_flags := Bits(0)
|
||||
if (nClients > 1) {
|
||||
// issue self-probes for uncached read xacts to facilitate I$ coherence
|
||||
val probe_self = Bool(true) //co.needsSelfProbe(io.inner.acquire.bits.payload)
|
||||
val myflag = Mux(probe_self, Bits(0), UIntToOH(c_acq.header.src(log2Up(nClients)-1,0)))
|
||||
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
||||
}
|
||||
// issue self-probes for uncached read xacts to facilitate I$ coherence
|
||||
val probe_self = co.requiresSelfProbe(io.inner.acquire.bits.payload)
|
||||
val myflag = Mux(probe_self, Bits(0), UIntToOH(c_acq.header.src(log2Up(nClients)-1,0)))
|
||||
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
||||
|
||||
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) && (state != s_idle)
|
||||
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) && (state != s_idle) && !collect_inner_data
|
||||
io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) && (state != s_idle)
|
||||
|
||||
io.outer.acquire.valid := Bool(false)
|
||||
@ -244,6 +286,14 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
|
||||
io.inner.acquire.ready := Bool(false)
|
||||
io.inner.release.ready := Bool(false)
|
||||
|
||||
when(collect_inner_data) {
|
||||
io.inner.acquire.ready := Bool(true)
|
||||
when(io.inner.acquire.valid) {
|
||||
data_ptrs(inner_data_cnt) := c_acq.payload.data
|
||||
}
|
||||
when(inner_data_done) { collect_inner_data := Bool(false) }
|
||||
}
|
||||
|
||||
switch (state) {
|
||||
is(s_idle) {
|
||||
io.inner.acquire.ready := Bool(true)
|
||||
@ -252,14 +302,13 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
|
||||
when( io.inner.acquire.valid ) {
|
||||
xact := c_acq.payload
|
||||
init_client_id := c_acq.header.src
|
||||
data_ptrs(UInt(0)) := c_acq.payload.data
|
||||
collect_inner_data := co.messageHasData(c_acq.payload)
|
||||
probe_flags := probe_initial_flags
|
||||
if(nClients > 1) {
|
||||
release_count := PopCount(probe_initial_flags)
|
||||
state := Mux(probe_initial_flags.orR, s_probe,
|
||||
Mux(needs_outer_write, s_mem_write,
|
||||
Mux(needs_outer_read, s_mem_read, s_make_grant)))
|
||||
} else state := Mux(needs_outer_write, s_mem_write,
|
||||
Mux(needs_outer_read, s_mem_read, s_make_grant))
|
||||
release_count := PopCount(probe_initial_flags)
|
||||
state := Mux(probe_initial_flags.orR, s_probe,
|
||||
Mux(needs_outer_write, s_mem_write,
|
||||
Mux(needs_outer_read, s_mem_read, s_make_grant)))
|
||||
}
|
||||
}
|
||||
is(s_probe) {
|
||||
@ -276,15 +325,17 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
|
||||
io.outer.acquire.bits.payload := outer_write_rel
|
||||
when(io.outer.acquire.ready) {
|
||||
io.inner.release.ready := Bool(true)
|
||||
if(nClients > 1) release_count := release_count - UInt(1)
|
||||
when(release_count === UInt(1)) {
|
||||
state := Mux(pending_outer_write, s_mem_write,
|
||||
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||||
when(outer_data_done) {
|
||||
release_count := release_count - UInt(1)
|
||||
when(release_count === UInt(1)) {
|
||||
state := Mux(pending_outer_write, s_mem_write,
|
||||
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||||
}
|
||||
}
|
||||
}
|
||||
} .otherwise {
|
||||
io.inner.release.ready := Bool(true)
|
||||
if(nClients > 1) release_count := release_count - UInt(1)
|
||||
release_count := release_count - UInt(1)
|
||||
when(release_count === UInt(1)) {
|
||||
state := Mux(pending_outer_write, s_mem_write,
|
||||
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||||
@ -300,9 +351,9 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
|
||||
}
|
||||
}
|
||||
is(s_mem_write) {
|
||||
io.outer.acquire.valid := Bool(true)
|
||||
io.outer.acquire.valid := (if(tlDataBeats == 1) Bool(true) else !collect_inner_data || (outer_data_cnt < inner_data_cnt))
|
||||
io.outer.acquire.bits.payload := outer_write_acq
|
||||
when(io.outer.acquire.ready) {
|
||||
when(outer_data_done) {
|
||||
state := Mux(pending_outer_read, s_mem_read, s_make_grant)
|
||||
}
|
||||
}
|
||||
|
||||
88
uncore/src/main/scala/util.scala
Normal file
88
uncore/src/main/scala/util.scala
Normal file
@ -0,0 +1,88 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package uncore
|
||||
|
||||
import Chisel._
|
||||
import scala.math._
|
||||
|
||||
object MuxBundle {
|
||||
def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
|
||||
mapping.reverse.foldLeft(default)((b, a) => Mux(a._1, a._2, b))
|
||||
}
|
||||
}
|
||||
|
||||
// Produces 0-width value when counting to 1
|
||||
class ZCounter(val n: Int) {
|
||||
val value = Reg(init=UInt(0, log2Ceil(n)))
|
||||
def inc(): Bool = {
|
||||
if (n == 1) Bool(true)
|
||||
else {
|
||||
val wrap = value === UInt(n-1)
|
||||
value := Mux(Bool(!isPow2(n)) && wrap, UInt(0), value + UInt(1))
|
||||
wrap
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
object ZCounter {
|
||||
def apply(n: Int) = new ZCounter(n)
|
||||
def apply(cond: Bool, n: Int): (UInt, Bool) = {
|
||||
val c = new ZCounter(n)
|
||||
var wrap: Bool = null
|
||||
when (cond) { wrap = c.inc() }
|
||||
(c.value, cond && wrap)
|
||||
}
|
||||
}
|
||||
|
||||
class FlowThroughSerializer[T <: HasTileLinkData](gen: LogicalNetworkIO[T], n: Int, doSer: T => Bool) extends Module {
|
||||
val io = new Bundle {
|
||||
val in = Decoupled(gen.clone).flip
|
||||
val out = Decoupled(gen.clone)
|
||||
val cnt = UInt(OUTPUT, log2Up(n))
|
||||
val done = Bool(OUTPUT)
|
||||
}
|
||||
val narrowWidth = io.in.bits.payload.data.getWidth / n
|
||||
require(io.in.bits.payload.data.getWidth % narrowWidth == 0)
|
||||
|
||||
if(n == 1) {
|
||||
io.in <> io.out
|
||||
io.cnt := UInt(width = 0)
|
||||
io.done := Bool(true)
|
||||
} else {
|
||||
val cnt = Reg(init=UInt(0, width = log2Up(n)))
|
||||
val wrap = cnt === UInt(n-1)
|
||||
val rbits = Reg(init=io.in.bits)
|
||||
val active = Reg(init=Bool(false))
|
||||
|
||||
val shifter = Vec.fill(n){Bits(width = narrowWidth)}
|
||||
(0 until n).foreach {
|
||||
i => shifter(i) := rbits.payload.data((i+1)*narrowWidth-1,i*narrowWidth)
|
||||
}
|
||||
|
||||
io.done := Bool(false)
|
||||
io.cnt := cnt
|
||||
io.in.ready := !active
|
||||
io.out.valid := active || io.in.valid
|
||||
io.out.bits := io.in.bits
|
||||
when(!active && io.in.valid) {
|
||||
when(doSer(io.in.bits.payload)) {
|
||||
cnt := Mux(io.out.ready, UInt(1), UInt(0))
|
||||
rbits := io.in.bits
|
||||
active := Bool(true)
|
||||
}
|
||||
io.done := !doSer(io.in.bits.payload)
|
||||
}
|
||||
when(active) {
|
||||
io.out.bits := rbits
|
||||
io.out.bits.payload.data := shifter(cnt)
|
||||
when(io.out.ready) {
|
||||
cnt := cnt + UInt(1)
|
||||
when(wrap) {
|
||||
cnt := UInt(0)
|
||||
io.done := Bool(true)
|
||||
active := Bool(false)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user