riscv/rocket-chip
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replace NASTIMasterIO and NASTISlaveIO with NASTIIO

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This commit is contained in:
Howard Mao 2015-09-24 16:58:20 -07:00
parent b4d21148ec
commit 3b86790c3f
2 changed files with 7 additions and 7 deletions
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4
uncore/src/main/scala/rtc.scala
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@ -1,10 +1,10 @@
package uncore
import Chisel._
import junctions.{NASTIMasterIO, NASTIAddrHashMap, SMIIO}
import junctions.{NASTIIO, NASTIAddrHashMap, SMIIO}
class RTC(pcr_MTIME: Int) extends Module {
val io = new NASTIMasterIO
val io = new NASTIIO
private val nCores = params(HTIFNCores)
private val addrMap = params(NASTIAddrHashMap)

10
uncore/src/main/scala/tilelink.scala
View File

@ -1369,15 +1369,15 @@ class ClientTileLinkIOUnwrapper extends TLModule {
io.in.probe.valid := Bool(false)
}
class NASTIMasterIOTileLinkIOConverterInfo extends TLBundle {
class NASTIIOTileLinkIOConverterInfo extends TLBundle {
val byteOff = UInt(width = tlByteAddrBits)
val subblock = Bool()
}
class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters {
class NASTIIOTileLinkIOConverter extends TLModule with NASTIParameters {
val io = new Bundle {
val tl = new ClientUncachedTileLinkIO().flip
val nasti = new NASTIMasterIO
val nasti = new NASTIIO
}
private def opSizeToXSize(ops: UInt) = MuxLookup(ops, UInt("b111"), Seq(
@ -1393,7 +1393,7 @@ class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters {
val dstIdBits = params(LNHeaderBits)
require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NASTIMasterIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)
require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NASTIIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)
io.tl.acquire.ready := Bool(false)
@ -1419,7 +1419,7 @@ class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters {
val tl_done_out = Reg(init=Bool(false))
val roq = Module(new ReorderQueue(
new NASTIMasterIOTileLinkIOConverterInfo,
new NASTIIOTileLinkIOConverterInfo,
nastiRIdBits, tlMaxClientsPerPort))
val (nasti_cnt_out, nasti_wrap_out) = Counter(