riscv/rocket-chip
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guard all writes to data ram with masks

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This commit is contained in:
Yunsup Lee 2015-03-17 20:24:04 -07:00
parent d14efce0b4
commit 9de5161d7a
1 changed files with 2 additions and 1 deletions
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3
uncore/src/main/scala/cache.scala
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@ -686,6 +686,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
wmask & Mux(xact.isBuiltInType(Acquire.putAtomicType),
amoalu.io.out << xact.amo_shift_bits(),
new_data)
wmask_buffer(beat) := SInt(-1)
when(xact.is(Acquire.putAtomicType) && xact.addr_beat === beat) { amo_result := old_data }
}
val mergeDataInternal = mergeData(rowBits) _
@ -779,7 +780,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
io.data.write.bits.way_en := xact_way_en
io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB)
io.data.write.bits.addr_beat := curr_write_beat
io.data.write.bits.wmask := SInt(-1)
io.data.write.bits.wmask := wmask_buffer(curr_write_beat)
io.data.write.bits.data := data_buffer(curr_write_beat)
io.meta.read.valid := Bool(false)
io.meta.read.bits.id := UInt(trackerId)