parameterize metadataarray
This commit is contained in:
Henry Cook
parent
0237229921
commit
45172f1f37
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@ -14,8 +14,6 @@ trait CacheConfig {
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def offbits: Int
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def untagbits: Int
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def rowbits: Int
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def metabits: Int
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def statebits: Int
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}
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case class L2CacheConfig(
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@ -45,7 +43,6 @@ case class L2CacheConfig(
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def rowoffbits = log2Up(rowbytes)
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def refillcycles = tl.dataBits/(rowbits)
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def statebits = log2Up(states)
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def metabits = statebits + tagbits
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require(states > 0)
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require(isPow2(sets))
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@ -79,54 +76,61 @@ class RandomReplacement(implicit val cacheconf: CacheConfig) extends Replacement
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def hit = {}
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}
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object MetaData {
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def apply(tag: Bits, state: UInt)(implicit cacheconf: CacheConfig) = {
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val meta = new MetaData
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meta.state := state
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meta.tag := tag
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meta
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}
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}
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class MetaData(implicit val cacheconf: CacheConfig) extends CacheBundle {
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val state = UInt(width = cacheconf.statebits)
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abstract class MetaData(implicit val cacheconf: CacheConfig) extends CacheBundle {
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val tag = Bits(width = cacheconf.tagbits)
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}
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class L2MetaData(implicit val l2cacheconf: L2CacheConfig) extends MetaData
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with L2CacheBundle {
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val state = UInt(width = l2cacheconf.statebits)
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val sharers = Bits(width = l2cacheconf.tl.ln.nClients)
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}
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/*
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class L3MetaData(implicit conf: L3CacheConfig) extends MetaData()(conf) {
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val cstate = UInt(width = cacheconf.cstatebits)
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val mstate = UInt(width = cacheconf.mstatebits)
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val sharers = Bits(width = cacheconf.tl.ln.nClients)
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}
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*/
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class MetaReadReq(implicit val cacheconf: CacheConfig) extends CacheBundle {
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val idx = Bits(width = cacheconf.idxbits)
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}
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class MetaWriteReq(implicit conf: CacheConfig) extends MetaReadReq()(conf) {
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class MetaWriteReq[T <: MetaData](gen: T)(implicit conf: CacheConfig) extends MetaReadReq {
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val way_en = Bits(width = conf.ways)
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val data = new MetaData()
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val data = gen.clone
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override def clone = new MetaWriteReq(gen)(conf).asInstanceOf[this.type]
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}
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class MetaDataArray(implicit conf: CacheConfig) extends Module {
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class MetaDataArray[T <: MetaData](resetMeta: T)(implicit conf: CacheConfig) extends Module {
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implicit val tl = conf.tl
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def gen = resetMeta.clone
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val io = new Bundle {
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val read = Decoupled(new MetaReadReq).flip
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val write = Decoupled(new MetaWriteReq).flip
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val resp = Vec.fill(conf.ways){(new MetaData).asOutput}
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val write = Decoupled(new MetaWriteReq(gen)).flip
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val resp = Vec.fill(conf.ways){gen.asOutput}
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}
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val metabits = resetMeta.getWidth
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val rst_cnt = Reg(init=UInt(0, log2Up(conf.sets+1)))
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val rst = rst_cnt < UInt(conf.sets)
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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val tags = Mem(UInt(width = conf.metabits*conf.ways), conf.sets, seqRead = true)
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val tags = Mem(UInt(width = metabits*conf.ways), conf.sets, seqRead = true)
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when (rst || io.write.valid) {
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val addr = Mux(rst, rst_cnt, io.write.bits.idx)
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val data = Cat(Mux(rst, tl.co.newStateOnFlush, io.write.bits.data.state), io.write.bits.data.tag)
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val data = Mux(rst, resetMeta, io.write.bits.data).toBits
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val mask = Mux(rst, SInt(-1), io.write.bits.way_en)
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tags.write(addr, Fill(conf.ways, data), FillInterleaved(conf.metabits, mask))
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tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask))
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}
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val tag = tags(RegEnable(io.read.bits.idx, io.read.valid))
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for (w <- 0 until conf.ways) {
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val m = tag(conf.metabits*(w+1)-1, conf.metabits*w)
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io.resp(w).state := m >> UInt(conf.tagbits)
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io.resp(w).tag := m
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val m = tag(metabits*(w+1)-1, metabits*w)
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io.resp(w) := gen.fromBits(m)
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}
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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@ -165,23 +169,23 @@ class L2DataArray(implicit conf: L2CacheConfig) extends Module {
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io.write.ready := Bool(true)
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}
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trait InternalRequestState extends CacheBundle {
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trait L2InternalRequestState extends L2CacheBundle {
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val tag_match = Bool()
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val old_meta = new MetaData
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val way_en = Bits(width = cacheconf.ways)
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val old_meta = new L2MetaData
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val way_en = Bits(width = l2cacheconf.ways)
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}
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class InternalAcquire(implicit val cacheconf: CacheConfig) extends Acquire()(cacheconf.tl)
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with InternalRequestState
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class L2InternalAcquire(implicit val l2cacheconf: L2CacheConfig) extends Acquire()(l2cacheconf.tl)
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with L2InternalRequestState
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class InternalRelease(implicit val cacheconf: CacheConfig) extends Release()(cacheconf.tl)
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with InternalRequestState
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class L2InternalRelease(implicit val l2cacheconf: L2CacheConfig) extends Release()(l2cacheconf.tl)
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with L2InternalRequestState
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class InternalTileLinkIO(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle {
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implicit val (tl, ln) = (l2cacheconf.tl, l2cacheconf.tl.ln)
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val acquire = new DecoupledIO(new LogicalNetworkIO(new InternalAcquire))
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val acquire = new DecoupledIO(new LogicalNetworkIO(new L2InternalAcquire))
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val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip
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val release = new DecoupledIO(new LogicalNetworkIO(new InternalRelease))
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val release = new DecoupledIO(new LogicalNetworkIO(new L2InternalRelease))
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val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
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val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
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}
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@ -191,6 +195,21 @@ class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceA
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val tshrfile = Module(new TSHRFile(bankId))
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// tags
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val meta = Module(new MetaDataArray(new L2MetaData))
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// data
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val data = Module(new L2DataArray)
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// replacement policy
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val replacer = new RandomReplacement
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/*
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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*/
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tshrfile.io.inner <> io.inner
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io.outer <> tshrfile.io.outer
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io.incoherent <> tshrfile.io.incoherent
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@ -204,9 +223,9 @@ class TSHRFile(bankId: Int)(implicit conf: L2CacheConfig) extends Module {
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val outer = new UncachedTileLinkIO
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val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
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val meta_read_req = Decoupled(new MetaReadReq)
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val meta_write_req = Decoupled(new MetaWriteReq)
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val data_read_req = Decoupled(new MetaReadReq)
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val data_write_req = Decoupled(new MetaWriteReq)
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val meta_write_req = Decoupled(new MetaWriteReq(new L2MetaData))
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val data_read_req = Decoupled(new L2DataReadReq)
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val data_write_req = Decoupled(new L2DataWriteReq)
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}
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// Create TSHRs for outstanding transactions
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