riscv/rocket-chip
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re-merge mem resp queues

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This commit is contained in:
Henry Cook 2015-03-17 12:22:57 -07:00
parent 1471d9debc
commit 9bedde9a8a
1 changed files with 4 additions and 14 deletions
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18
uncore/src/main/scala/memserdes.scala
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@ -544,21 +544,11 @@ class MemPipeIOMemIOConverter(numRequests: Int, refillCycles: Int) extends Modul
io.mem.req_data <> io.cpu.req_data
// Have separate queues to allow for different mem implementations
val resp_dataq = Module((new HellaQueue(numEntries)) { new MemData })
resp_dataq.io.enq.valid := io.mem.resp.valid
resp_dataq.io.enq.bits.data := io.mem.resp.bits.data
val resp_data_q = Module((new HellaQueue(numEntries)) { new MemResp })
resp_data_q.io.enq <> io.mem.resp
io.cpu.resp <> resp_data_q.io.deq
val resp_tagq = Module((new HellaQueue(numEntries)) { new MemTag })
resp_tagq.io.enq.valid := io.mem.resp.valid
resp_tagq.io.enq.bits.tag := io.mem.resp.bits.tag
io.cpu.resp.valid := resp_dataq.io.deq.valid && resp_tagq.io.deq.valid
io.cpu.resp.bits.data := resp_dataq.io.deq.bits.data
io.cpu.resp.bits.tag := resp_tagq.io.deq.bits.tag
resp_dataq.io.deq.ready := io.cpu.resp.ready
resp_tagq.io.deq.ready := io.cpu.resp.ready
inc := resp_dataq.io.deq.fire()
inc := resp_data_q.io.deq.fire()
dec := io.mem.req_cmd.fire() && !io.mem.req_cmd.bits.rw
}