Add Wire() wrap

uncore/src/main/scala/cache.scala

@@ -115,7 +115,7 @@ abstract class ReplacementPolicy {
 }
 
 class RandomReplacement(ways: Int) extends ReplacementPolicy {
-  private val replace = Bool()
+  private val replace = Wire(Bool())
   replace := Bool(false)
   val lfsr = LFSR16(replace)
 
@@ -224,7 +224,7 @@ class L2Metadata extends Metadata with L2HellaCacheParameters {
 
 object L2Metadata {
   def apply(tag: Bits, coh: HierarchicalMetadata) = {
-    val meta = new L2Metadata
+    val meta = Wire(new L2Metadata)
     meta.tag := tag
     meta.coh := coh
     meta

uncore/src/main/scala/htif.scala

@@ -247,7 +247,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
   }
 
   val scr_addr = addr(log2Up(nSCR)-1, 0)
-  val scr_rdata = Vec.fill(io.scr.rdata.size){Bits(width = 64)}
+  val scr_rdata = Wire(Vec(Bits(width=64), io.scr.rdata.size))
   for (i <- 0 until scr_rdata.size)
     scr_rdata(i) := io.scr.rdata(i)
   scr_rdata(0) := UInt(nCores)

uncore/src/main/scala/memserdes.scala

@@ -467,7 +467,7 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module
   val io = new QueueIO(data, entries)
   require(entries > 1)
 
-  val do_flow = Bool()
+  val do_flow = Wire(Bool())
   val do_enq = io.enq.fire() && !do_flow
   val do_deq = io.deq.fire() && !do_flow
 
@@ -559,7 +559,7 @@ class MemIOArbiter(val arbN: Int) extends MIFModule {
 
 object MemIOMemPipeIOConverter {
   def apply(in: MemPipeIO): MemIO = {
-    val out = new MemIO().asDirectionless
+    val out = Wire(new MemIO())
     in.resp.valid := out.resp.valid
     in.resp.bits := out.resp.bits
     out.resp.ready := Bool(true)
@@ -582,8 +582,8 @@ class MemPipeIOMemIOConverter(numRequests: Int) extends MIFModule {
   val numEntries = numRequests * mifDataBeats
   val size = log2Down(numEntries) + 1
 
-  val inc = Bool()
-  val dec = Bool()
+  val inc = Wire(Bool())
+  val dec = Wire(Bool())
   val count = Reg(init=UInt(numEntries, size))
   val watermark = count >= UInt(mifDataBeats)
 

uncore/src/main/scala/metadata.scala

@@ -150,7 +150,7 @@ class ClientMetadata extends CoherenceMetadata {
 /** Factories for ClientMetadata, including on reset */
 object ClientMetadata {
   def apply(state: UInt) = {
-    val meta = new ClientMetadata
+    val meta = Wire(new ClientMetadata)
     meta.state := state
     meta
   }
@@ -288,13 +288,13 @@ class ManagerMetadata extends CoherenceMetadata {
 /** Factories for ManagerMetadata, including on reset */
 object ManagerMetadata {
   def apply(sharers: UInt, state: UInt = UInt(width = 0)) = {
-    val meta = new ManagerMetadata
+    val meta = Wire(new ManagerMetadata)
     //meta.state := state TODO: Fix 0-width wires in Chisel 
     meta.sharers := sharers
     meta
   }
   def apply() = {
-    val meta = new ManagerMetadata
+    val meta = Wire(new ManagerMetadata)
     //meta.state := UInt(width = 0) TODO: Fix 0-width wires in Chisel 
     meta.sharers := meta.co.dir.flush
     meta
@@ -321,7 +321,7 @@ class HierarchicalMetadata extends CoherenceMetadata {
 /** Factories for HierarchicalMetadata, including on reset */
 object HierarchicalMetadata {
   def apply(inner: ManagerMetadata, outer: ClientMetadata): HierarchicalMetadata = {
-    val m = new HierarchicalMetadata
+    val m = Wire(new HierarchicalMetadata)
     m.inner := inner
     m.outer := outer
     m

uncore/src/main/scala/network.scala

@@ -73,7 +73,7 @@ object DecoupledLogicalNetworkIOWrapper {
 
 object DecoupledLogicalNetworkIOUnwrapper {
   def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]]): DecoupledIO[T] = {
-    val out = Decoupled(in.bits.payload).asDirectionless
+    val out = Wire(Decoupled(in.bits.payload))
     out.valid := in.valid
     out.bits := in.bits.payload
     in.ready := out.ready

uncore/src/main/scala/tilelink.scala

@@ -257,7 +257,7 @@ object Acquire {
       addr_beat: UInt = UInt(0),
       data: UInt = UInt(0),
       union: UInt = UInt(0)): Acquire = {
-    val acq = new Acquire
+    val acq = Wire(new Acquire)
     acq.is_builtin_type := is_builtin_type
     acq.a_type := a_type
     acq.client_xact_id := client_xact_id
@@ -269,7 +269,7 @@ object Acquire {
   }
   // Copy constructor
   def apply(a: Acquire): Acquire = {
-    val acq = new Acquire
+    val acq = Wire(new Acquire)
     acq := a
     acq
   }
@@ -513,13 +513,13 @@ class ProbeToDst extends Probe with HasClientId
   */
 object Probe {
   def apply(p_type: UInt, addr_block: UInt): Probe = {
-    val prb = new Probe
+    val prb = Wire(new Probe)
     prb.p_type := p_type
     prb.addr_block := addr_block
     prb
   }
   def apply(dst: UInt, p_type: UInt, addr_block: UInt): ProbeToDst = {
-    val prb = new ProbeToDst
+    val prb = Wire(new ProbeToDst)
     prb.client_id := dst
     prb.p_type := p_type
     prb.addr_block := addr_block
@@ -574,7 +574,7 @@ object Release {
       addr_block: UInt,
       addr_beat: UInt = UInt(0),
       data: UInt = UInt(0)): Release = {
-    val rel = new Release
+    val rel = Wire(new Release)
     rel.r_type := r_type
     rel.client_xact_id := client_xact_id
     rel.addr_block := addr_block
@@ -613,7 +613,7 @@ class Grant extends ManagerToClientChannel
   def isVoluntary(dummy: Int = 0): Bool = isBuiltInType() && (g_type === Grant.voluntaryAckType)
   def requiresAck(dummy: Int = 0): Bool = !Bool(tlNetworkPreservesPointToPointOrdering) && !isVoluntary()
   def makeFinish(dummy: Int = 0): Finish = {
-    val f = Bundle(new Finish, { case TLMaxManagerXacts => tlMaxManagerXacts })
+    val f = Wire(Bundle(new Finish, { case TLMaxManagerXacts => tlMaxManagerXacts }))
     f.manager_xact_id := this.manager_xact_id
     f
   }
@@ -671,7 +671,7 @@ object Grant {
       manager_xact_id: UInt,
       addr_beat: UInt = UInt(0),
       data: UInt = UInt(0)): GrantToDst = {
-    val gnt = new GrantToDst
+    val gnt = Wire(new GrantToDst)
     gnt.client_id := dst
     gnt.is_builtin_type := is_builtin_type
     gnt.g_type := g_type
@@ -904,7 +904,7 @@ object ClientTileLinkHeaderCreator {
       in: DecoupledIO[T],
       clientId: Int,
       addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
-    val out = new DecoupledIO(new LogicalNetworkIO(in.bits)).asDirectionless
+    val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
     out.bits.payload := in.bits
     out.bits.header.src := UInt(clientId)
     out.bits.header.dst := addrConvert(in.bits.addr_block)
@@ -943,7 +943,7 @@ object ManagerTileLinkHeaderCreator {
       in: DecoupledIO[T],
       managerId: Int,
       idConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
-    val out = new DecoupledIO(new LogicalNetworkIO(in.bits)).asDirectionless
+    val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
     out.bits.payload := in.bits
     out.bits.header.src := UInt(managerId)
     out.bits.header.dst := idConvert(in.bits.client_id)