riscv/rocket-chip
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disconnect unused outer network headers

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This commit is contained in:
Henry Cook 2014-12-22 18:50:37 -08:00
parent 2ef4357ca8
commit e62c71203e
2 changed files with 0 additions and 4 deletions
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2
uncore/src/main/scala/cache.scala
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@ -413,7 +413,6 @@ class L2WritebackUnit(trackerId: Int, bankId: Int, innerId: String, outerId: Str
UInt(trackerId),
xact_data(outer_data_write_cnt)),
{ case TLId => outerId })
io.outer.acquire.bits.header.src := UInt(bankId)
io.outer.grant.ready := Bool(false) // Never gets mgnts
io.inner.probe.valid := Bool(false)
@ -712,7 +711,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
io.outer.acquire.valid := Bool(false)
io.outer.acquire.bits.payload := outer_read //default
io.outer.acquire.bits.header.src := UInt(bankId)
io.outer.grant.ready := Bool(true) //grant.data -> xact.data
io.inner.probe.valid := Bool(false)

2
uncore/src/main/scala/uncore.scala
View File

@ -198,7 +198,6 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, oute
xact_client_xact_id,
UInt(trackerId))
io.outer.acquire.bits.header.src := UInt(bankId)
io.outer.acquire.bits.payload := Bundle(UncachedWrite(
xact_addr,
UInt(trackerId),
@ -286,7 +285,6 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
io.outer.acquire.valid := Bool(false)
io.outer.acquire.bits.payload := outer_read //default
io.outer.acquire.bits.header.src := UInt(bankId)
io.outer.grant.ready := io.inner.grant.ready
io.inner.probe.valid := Bool(false)