Fix BroadcastHub AcquiteTracker allocation bug and clean up tracker wiring
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c03976896e
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@ -40,53 +40,53 @@ class L2BroadcastHub(bankId: Int) extends ManagerCoherenceAgent
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trackerList.map(_.io.incoherent := io.incoherent.toBits)
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// Queue to store impending Put data
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val acquire = io.inner.acquire
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val sdq = Vec.fill(sdqDepth){ Reg(io.iacq().data) }
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val sdq_val = Reg(init=Bits(0, sdqDepth))
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val sdq_alloc_id = PriorityEncoder(~sdq_val)
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val sdq_rdy = !sdq_val.andR
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val sdq_enq = acquire.fire() && acquire.bits.payload.hasData()
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val sdq = Vec.fill(sdqDepth){ Reg(io.inner.acquire.bits.payload.data) }
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when (sdq_enq) { sdq(sdq_alloc_id) := acquire.bits.payload.data }
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val sdq_enq = io.inner.acquire.fire() && io.iacq().hasData()
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when (sdq_enq) { sdq(sdq_alloc_id) := io.iacq().data }
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// Handle acquire transaction initiation
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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val block_acquires = any_acquire_conflict
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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t.acquire.bits.payload.data := DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
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t.acquire.valid := alloc_arb.io.in(i).ready
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val trackerAcquireIOs = trackerList.map(_.io.inner.acquire)
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val acquireMatchList = trackerList.map(_.io.has_acquire_match)
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val any_acquire_matches = acquireMatchList.reduce(_||_)
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val alloc_idx = Vec(alloc_arb.io.in.map(_.ready)).lastIndexWhere{b: Bool => b}
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val match_idx = Vec(acquireMatchList).indexWhere{b: Bool => b}
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val acquire_idx = Mux(any_acquire_matches, match_idx, alloc_idx)
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trackerAcquireIOs.zip(alloc_arb.io.in).zipWithIndex.foreach {
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case((tracker, arb), i) =>
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arb.valid := tracker.ready
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tracker.bits := io.inner.acquire.bits
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tracker.bits.payload.data :=
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DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
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tracker.valid := arb.ready && (acquire_idx === UInt(i))
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}
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acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && sdq_rdy && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && sdq_rdy && !block_acquires
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val block_acquires = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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io.inner.acquire.ready := trackerAcquireIOs.map(_.ready).reduce(_||_) &&
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sdq_rdy && !block_acquires
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alloc_arb.io.out.ready := io.inner.acquire.valid && sdq_rdy && !block_acquires
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// Queue to store impending Voluntary Release data
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val release = io.inner.release
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val voluntary = release.bits.payload.isVoluntary()
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val vwbdq_enq = release.fire() && voluntary && release.bits.payload.hasData()
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val voluntary = io.irel().isVoluntary()
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val vwbdq_enq = io.inner.release.fire() && voluntary && io.irel().hasData()
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val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, innerDataBeats) //TODO Zero width
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val vwbdq = Vec.fill(innerDataBeats){ Reg(release.bits.payload.data) } //TODO Assumes nReleaseTransactors == 1
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when(vwbdq_enq) { vwbdq(rel_data_cnt) := release.bits.payload.data }
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val vwbdq = Vec.fill(innerDataBeats){ Reg(io.irel().data) } //TODO Assumes nReleaseTransactors == 1
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when(vwbdq_enq) { vwbdq(rel_data_cnt) := io.irel().data }
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// Handle releases, which might be voluntary and might have data
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val release_idx = Vec(trackerList.map(_.io.has_release_match)).indexWhere{b: Bool => b}
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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t.release.bits := release.bits
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t.release.bits.payload.data := (if (i < nReleaseTransactors)
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DataQueueLocation(rel_data_cnt, inVolWBQueue)
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else DataQueueLocation(UInt(0), inClientReleaseQueue)).toBits
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t.release.valid := release.valid && (release_idx === UInt(i))
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val trackerReleaseIOs = trackerList.map(_.io.inner.release)
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trackerReleaseIOs.zipWithIndex.foreach {
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case(tracker, i) =>
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tracker.bits := io.inner.release.bits
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tracker.bits.payload.data := DataQueueLocation(rel_data_cnt,
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(if(i < nReleaseTransactors) inVolWBQueue
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else inClientReleaseQueue)).toBits
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tracker.valid := io.inner.release.valid && (release_idx === UInt(i))
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}
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx)
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// Wire finished transaction acks
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val ack = io.inner.finish
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trackerList.map(_.io.inner.finish.valid := ack.valid)
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trackerList.map(_.io.inner.finish.bits := ack.bits)
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ack.ready := Bool(true)
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io.inner.release.ready := Vec(trackerReleaseIOs.map(_.ready)).read(release_idx)
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// Wire probe requests and grant reply to clients, finish acks from clients
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// Note that we bypass the Grant data subbundles
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@ -107,7 +107,7 @@ class L2BroadcastHub(bankId: Int) extends ManagerCoherenceAgent
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val free_sdq = io.outer.acquire.fire() &&
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io.outer.acquire.bits.payload.hasData() &&
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outer_data_ptr.loc === inStoreQueue
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io.outer.acquire.bits.payload.data := MuxLookup(outer_data_ptr.loc, release.bits.payload.data, Array(
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io.outer.acquire.bits.payload.data := MuxLookup(outer_data_ptr.loc, io.irel().data, Array(
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inStoreQueue -> sdq(outer_data_ptr.idx),
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inVolWBQueue -> vwbdq(outer_data_ptr.idx)))
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io.outer <> outer_arb.io.out
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@ -216,8 +216,9 @@ class BroadcastAcquireTracker(trackerId: Int, bankId: Int) extends BroadcastXact
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val coh = ManagerMetadata.onReset
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assert(!(state != s_idle && xact.isBuiltInType() &&
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Vec(Acquire.getType, Acquire.putType, Acquire.putAtomicType).contains(xact.a_type)),
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"Broadcast Hub does not support PutAtomics or subblock Gets/Puts") // TODO
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Vec(Acquire.getType, Acquire.putType, Acquire.putAtomicType,
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Acquire.prefetchType).contains(xact.a_type)),
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"Broadcast Hub does not support PutAtomics, subblock Gets/Puts, or prefetches") // TODO
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val release_count = Reg(init=UInt(0, width = log2Up(nCoherentClients+1)))
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val pending_probes = Reg(init=Bits(0, width = nCoherentClients))
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@ -238,17 +239,18 @@ class BroadcastAcquireTracker(trackerId: Int, bankId: Int) extends BroadcastXact
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val ognt_data_done = connectIncomingDataBeatCounter(io.outer.grant)
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val pending_ognt_ack = Reg(init=Bool(false))
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val pending_outer_write = xact.hasData()
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val pending_outer_read = io.ignt().hasData()
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val pending_outer_write_ = io.iacq().hasData()
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val pending_outer_read = io.ignt().hasData()
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val pending_outer_read_ = coh.makeGrant(io.iacq(), UInt(trackerId)).hasData()
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io.has_acquire_conflict := xact.conflicts(io.iacq()) &&
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!collect_iacq_data &&
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(state != s_idle)
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io.has_release_match := xact.conflicts(io.irel()) &&
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!io.irel().isVoluntary() &&
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(state != s_idle)
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io.has_acquire_match := Bool(false)
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(state != s_idle) &&
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!collect_iacq_data
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io.has_acquire_match := xact.conflicts(io.iacq()) &&
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collect_iacq_data
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io.has_release_match := xact.conflicts(io.irel()) &&
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!io.irel().isVoluntary() &&
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(state === s_probe)
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val outer_write_acq = Bundle(PutBlock(
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client_xact_id = UInt(trackerId),
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@ -282,6 +284,18 @@ class BroadcastAcquireTracker(trackerId: Int, bankId: Int) extends BroadcastXact
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io.inner.release.ready := Bool(false)
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io.inner.finish.ready := Bool(false)
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assert(!(state != s_idle && collect_iacq_data && io.inner.acquire.fire() &&
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io.inner.acquire.bits.header.src != xact_src),
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"AcquireTracker accepted data beat from different network source than initial request.")
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assert(!(state != s_idle && collect_iacq_data && io.inner.acquire.fire() &&
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io.iacq().client_xact_id != xact.client_xact_id),
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"AcquireTracker accepted data beat from different client transaction than initial request.")
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assert(!(state === s_idle && io.inner.acquire.fire() &&
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io.iacq().addr_beat != UInt(0)),
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"AcquireTracker initialized with a tail data beat.")
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when(collect_iacq_data) {
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io.inner.acquire.ready := Bool(true)
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when(io.inner.acquire.valid) {
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@ -356,33 +356,34 @@ class TSHRFile(bankId: Int) extends L2HellaCacheModule
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(trackerList.map(_.io.incoherent) :+ wb.io.incoherent).map( _ := io.incoherent.toBits)
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// Handle acquire transaction initiation
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val acquire = io.inner.acquire
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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val acquireList = trackerList.map(_.io.inner.acquire)
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val trackerAcquireIOs = trackerList.map(_.io.inner.acquire)
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val acquireMatchList = trackerList.map(_.io.has_acquire_match)
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val any_acquire_matches = acquireMatchList.reduce(_||_)
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val alloc_idx = Vec(alloc_arb.io.in.map(_.ready)).lastIndexWhere{b: Bool => b}
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val match_idx = Vec(acquireMatchList).indexWhere{b: Bool => b}
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val acquire_idx = Mux(any_acquire_matches, match_idx, alloc_idx)
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acquireList.zip(alloc_arb.io.in).zipWithIndex.map { case((acq, arb), i) =>
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arb.valid := acq.ready
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acq.bits := acquire.bits
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acq.valid := arb.ready && (acquire_idx === UInt(i))
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trackerAcquireIOs.zip(alloc_arb.io.in).zipWithIndex.foreach {
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case((tracker, arb), i) =>
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arb.valid := tracker.ready
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tracker.bits := io.inner.acquire.bits
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tracker.valid := arb.ready && (acquire_idx === UInt(i))
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}
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val block_acquires = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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acquire.ready := acquireList.map(_.ready).reduce(_||_) && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && !block_acquires
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io.inner.acquire.ready := trackerAcquireIOs.map(_.ready).reduce(_||_) &&
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!block_acquires
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alloc_arb.io.out.ready := io.inner.acquire.valid && !block_acquires
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// Wire releases from clients
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val release = io.inner.release
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val release_idx = Vec(trackerList.map(_.io.has_release_match) :+
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wb.io.has_release_match).indexWhere{b: Bool => b}
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val releaseList = trackerList.map(_.io.inner.release) :+ wb.io.inner.release
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releaseList.zipWithIndex.map { case(r, i) =>
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r.bits := release.bits
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r.valid := release.valid && (release_idx === UInt(i))
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val trackerReleaseIOs = trackerList.map(_.io.inner.release) :+ wb.io.inner.release
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trackerReleaseIOs.zipWithIndex.foreach {
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case(tracker, i) =>
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tracker.bits := io.inner.release.bits
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tracker.valid := io.inner.release.valid && (release_idx === UInt(i))
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}
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release.ready := Vec(releaseList.map(_.ready)).read(release_idx)
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io.inner.release.ready := Vec(trackerReleaseIOs.map(_.ready)).read(release_idx)
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// Wire probe requests and grant reply to clients, finish acks from clients
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doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe) :+ wb.io.inner.probe)
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@ -658,8 +659,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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!collect_iacq_data
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io.has_acquire_match := xact.conflicts(io.iacq()) &&
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collect_iacq_data
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io.has_release_match := !io.irel().isVoluntary() &&
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(xact.addr_block === io.irel().addr_block) &&
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io.has_release_match := xact.conflicts(io.irel()) &&
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!io.irel().isVoluntary() &&
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(state === s_probe)
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// If we're allocating in this cache, we can use the current metadata
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@ -729,6 +730,18 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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io.wb.req.bits.way_en := xact_way_en
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io.wb.req.bits.id := UInt(trackerId)
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assert(!(state != s_idle && collect_iacq_data && io.inner.acquire.fire() &&
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io.inner.acquire.bits.header.src != xact_src),
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"AcquireTracker accepted data beat from different network source than initial request.")
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assert(!(state != s_idle && collect_iacq_data && io.inner.acquire.fire() &&
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io.iacq().client_xact_id != xact.client_xact_id),
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"AcquireTracker accepted data beat from different client transaction than initial request.")
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assert(!(state === s_idle && io.inner.acquire.fire() &&
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io.iacq().addr_beat != UInt(0)),
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"AcquireTracker initialized with a tail data beat.")
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when(collect_iacq_data) {
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io.inner.acquire.ready := Bool(true)
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when(io.inner.acquire.valid) {
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