riscv/rocket-chip
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Merge branch 'master' of github.com:ucb-bar/uncore

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Howard Mao 2015-09-24 17:10:09 -07:00
commit 83740dfaa5
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uncore/src/main/scala/tilelink.scala
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@ -1261,7 +1261,7 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
val full = Bool(OUTPUT)
}
val roq_data = Reg(Vec(dType.clone, size))
val roq_data = Reg(Vec(dType.cloneType, size))
val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
val roq_free = Reg(init = Fill(size, Bits(1, 1)))