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Chisel3: Don't mix Mux types

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This commit is contained in:
Andrew Waterman 2015-07-11 14:05:39 -07:00
parent 5dc3da008e
commit e76a9d3493
1 changed files with 3 additions and 3 deletions
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6
uncore/src/main/scala/cache.scala
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@ -150,7 +150,7 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
val rst = rst_cnt < UInt(nSets)
val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
val wdata = Mux(rst, rstVal, io.write.bits.data).toBits
val wmask = Mux(rst, SInt(-1), io.write.bits.way_en).toUInt
val wmask = Mux(rst, SInt(-1), io.write.bits.way_en.toSInt).toUInt
when (rst) { rst_cnt := rst_cnt+UInt(1) }
val metabits = rstVal.getWidth
@ -881,9 +881,9 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
UInt(0))
pending_reads := Mux( // GetBlocks and custom types read all beats
io.iacq().isBuiltInType(Acquire.getBlockType) || !io.iacq().isBuiltInType(),
SInt(-1, width = innerDataBeats),
SInt(-1),
(addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire) |
addPendingBitWhenBeatHasPartialWritemask(io.inner.acquire)).toUInt)
addPendingBitWhenBeatHasPartialWritemask(io.inner.acquire)).toSInt).toUInt
pending_writes := addPendingBitWhenBeatHasDataAndAllocs(io.inner.acquire)
pending_resps := UInt(0)
pending_ignt_data := UInt(0)