Simplify release handling
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bfcfc3fe18
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d121af7f94
@ -303,17 +303,13 @@ class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCac
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// Handle releases, which might be voluntary and might have data
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val release = io.inner.release
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val voluntary = co.isVoluntary(release.bits.payload)
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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val block_releases = Bool(false)
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
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val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), conflict_idx)
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val release_idx = Vec(trackerList.map(_.io.has_release_match)).indexWhere{b: Bool => b}
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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t.release.bits := release.bits
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t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
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t.release.valid := release.valid && (release_idx === UInt(i))
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}
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx)
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// Wire finished transaction acks
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val finish = io.inner.finish
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@ -353,7 +349,7 @@ abstract class L2XactTracker(innerId: String, outerId: String) extends L2HellaCa
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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val tile_incoherent = Bits(INPUT, nClients)
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val has_acquire_conflict = Bool(OUTPUT)
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val has_release_conflict = Bool(OUTPUT)
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val has_release_match = Bool(OUTPUT)
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val data = new L2DataRWIO
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val meta = new L2MetaRWIO
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}
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@ -391,8 +387,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, ou
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Counter(io.data.write.fire(), tlDataBeats)
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io.has_acquire_conflict := Bool(false)
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io.has_release_conflict := co.isCoherenceConflict(xact_addr, c_rel.payload.addr) &&
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(state != s_idle)
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io.has_release_match := co.isVoluntary(c_rel.payload)
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io.outer.grant.ready := Bool(false)
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io.outer.acquire.valid := Bool(false)
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@ -541,9 +536,10 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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xact.addr(idxMSB,idxLSB) === c_acq.payload.addr(idxMSB,idxLSB) &&
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(state != s_idle) &&
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!collect_cacq_data
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io.has_release_conflict := (co.isCoherenceConflict(xact.addr, c_rel.payload.addr) ||
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co.isCoherenceConflict(wb_addr, c_rel.payload.addr)) &&
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(state != s_idle)
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io.has_release_match := !co.isVoluntary(c_rel.payload) &&
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(co.isCoherenceConflict(xact.addr, c_rel.payload.addr) ||
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co.isCoherenceConflict(wb_addr, c_rel.payload.addr)) &&
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(state === s_probe)
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val next_coh_on_release = co.masterMetadataOnRelease(
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c_rel.payload,
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@ -94,19 +94,16 @@ class L2BroadcastHub(bankId: Int, innerId: String, outerId: String) extends
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when(vwbdq_enq) { vwbdq(rel_data_cnt) := release.bits.payload.data }
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// Handle releases, which might be voluntary and might have data
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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val block_releases = Bool(false)
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
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val release_idx = Mux(voluntary, UInt(0), conflict_idx)
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val release_idx = Vec(trackerList.map(_.io.has_release_match)).indexWhere{b: Bool => b}
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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t.release.bits := release.bits
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t.release.bits.payload.data := (if (i < nReleaseTransactors)
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DataQueueLocation(rel_data_cnt, inVolWBQueue)
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else DataQueueLocation(UInt(0), inClientReleaseQueue)).toBits
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t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
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t.release.valid := release.valid && (release_idx === UInt(i))
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}
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx)
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// Wire finished transaction acks
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val ack = io.inner.finish
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@ -156,7 +153,7 @@ abstract class XactTracker(innerId: String, outerId: String) extends Module {
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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val tile_incoherent = Bits(INPUT, nClients)
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val has_acquire_conflict = Bool(OUTPUT)
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val has_release_conflict = Bool(OUTPUT)
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val has_release_match = Bool(OUTPUT)
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}
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val c_acq = io.inner.acquire.bits
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@ -184,8 +181,7 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, oute
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Counter(io.outer.acquire.fire() && co.messageHasData(io.outer.acquire.bits.payload), tlDataBeats)
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io.has_acquire_conflict := Bool(false)
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io.has_release_conflict := co.isCoherenceConflict(xact_addr, c_rel.payload.addr) &&
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(state != s_idle)
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io.has_release_match := co.isVoluntary(c_rel.payload)
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io.outer.grant.ready := Bool(false)
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io.outer.acquire.valid := Bool(false)
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@ -278,7 +274,8 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
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io.has_acquire_conflict := co.isCoherenceConflict(xact_addr, c_acq.payload.addr) &&
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(state != s_idle) &&
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!collect_inner_data
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io.has_release_conflict := co.isCoherenceConflict(xact_addr, c_rel.payload.addr) &&
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io.has_release_match := co.isCoherenceConflict(xact_addr, c_rel.payload.addr) &&
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!co.isVoluntary(c_rel.payload) &&
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(state != s_idle)
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val outer_write_acq = Bundle(UncachedWrite(xact_addr, UInt(trackerId), xact_data(outer_data_cnt)),
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