fix ready-valid mixup in TileLink unwrapper
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4389b9edb0
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1c135c1628
@ -1320,15 +1320,28 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
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val irel = io.in.release.bits
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val ognt = io.out.grant.bits
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val iacq_wait = needsRoqEnq(iacq) && !roqArb.io.in(0).ready
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val irel_wait = needsRoqEnq(irel) && !roqArb.io.in(1).ready
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val acq_roq_enq = needsRoqEnq(iacq)
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val rel_roq_enq = needsRoqEnq(irel)
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roqArb.io.in(0).valid := io.in.acquire.valid && needsRoqEnq(iacq)
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val acq_roq_ready = !acq_roq_enq || roqArb.io.in(0).ready
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val rel_roq_ready = !rel_roq_enq || roqArb.io.in(1).ready
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val acq_helper = DecoupledHelper(
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io.in.acquire.valid,
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acq_roq_ready,
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acqArb.io.in(0).ready)
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val rel_helper = DecoupledHelper(
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io.in.release.valid,
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rel_roq_ready,
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acqArb.io.in(1).ready)
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roqArb.io.in(0).valid := acq_helper.fire(acq_roq_ready, acq_roq_enq)
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roqArb.io.in(0).bits.data.voluntary := Bool(false)
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roqArb.io.in(0).bits.data.builtin := iacq.isBuiltInType()
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roqArb.io.in(0).bits.tag := iacq.client_xact_id
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acqArb.io.in(0).valid := io.in.acquire.valid && !iacq_wait
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acqArb.io.in(0).valid := acq_helper.fire(acqArb.io.in(0).ready)
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acqArb.io.in(0).bits := Acquire(
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is_builtin_type = Bool(true),
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a_type = Mux(iacq.isBuiltInType(),
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@ -1339,21 +1352,21 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
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data = iacq.data,
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union = Mux(iacq.isBuiltInType(),
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iacq.union, Cat(Acquire.fullWriteMask, Bool(false))))
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io.in.acquire.ready := acqArb.io.in(0).ready && !iacq_wait
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io.in.acquire.ready := acq_helper.fire(io.in.acquire.valid)
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roqArb.io.in(1).valid := io.in.release.valid && needsRoqEnq(iacq)
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roqArb.io.in(1).valid := rel_helper.fire(rel_roq_ready, rel_roq_enq)
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roqArb.io.in(1).bits.data.voluntary := irel.isVoluntary()
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roqArb.io.in(1).bits.data.builtin := Bool(true)
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roqArb.io.in(1).bits.tag := irel.client_xact_id
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acqArb.io.in(1).valid := io.in.release.valid && !irel_wait
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acqArb.io.in(1).valid := rel_helper.fire(acqArb.io.in(1).ready)
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acqArb.io.in(1).bits := PutBlock(
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client_xact_id = irel.client_xact_id,
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addr_block = irel.addr_block,
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addr_beat = irel.addr_beat,
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data = irel.data,
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wmask = Acquire.fullWriteMask)
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io.in.release.ready := acqArb.io.in(1).ready && !irel_wait
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io.in.release.ready := rel_helper.fire(io.in.release.valid)
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io.out.acquire <> acqArb.io.out
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@ -145,3 +145,13 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
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roq_free(roq_deq_addr) := Bool(true)
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}
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}
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object DecoupledHelper {
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def apply(rvs: Bool*) = new DecoupledHelper(rvs)
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}
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class DecoupledHelper(val rvs: Seq[Bool]) {
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def fire(exclude: Bool, includes: Bool*) = {
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(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
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}
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}
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