MetaData & friends moved to uncore/
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39681303b8
commit
f8f29c69b8
@ -74,34 +74,34 @@ class RandomReplacement(implicit val conf: CacheConfig) extends ReplacementPolic
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def hit = {}
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}
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object L2MetaData {
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object MetaData {
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def apply(tag: Bits, state: UInt)(implicit conf: CacheConfig) = {
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val meta = new L2MetaData
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val meta = new MetaData
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meta.state := state
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meta.tag := tag
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meta
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}
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}
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class L2MetaData(implicit val conf: CacheConfig) extends CacheBundle {
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class MetaData(implicit val conf: CacheConfig) extends CacheBundle {
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val state = UInt(width = conf.statebits)
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val tag = Bits(width = conf.tagbits)
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}
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class L2MetaReadReq(implicit val conf: CacheConfig) extends CacheBundle {
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class MetaReadReq(implicit val conf: CacheConfig) extends CacheBundle {
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val idx = Bits(width = conf.idxbits)
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}
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class L2MetaWriteReq(implicit conf: CacheConfig) extends L2MetaReadReq()(conf) {
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class MetaWriteReq(implicit conf: CacheConfig) extends MetaReadReq()(conf) {
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val way_en = Bits(width = conf.ways)
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val data = new L2MetaData()
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val data = new MetaData()
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}
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class L2MetaDataArray(implicit conf: CacheConfig) extends Module {
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class MetaDataArray(implicit conf: CacheConfig) extends Module {
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implicit val tl = conf.tl
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val io = new Bundle {
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val read = Decoupled(new L2MetaReadReq).flip
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val write = Decoupled(new L2MetaWriteReq).flip
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val resp = Vec.fill(conf.ways){(new L2MetaData).asOutput}
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val read = Decoupled(new MetaReadReq).flip
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val write = Decoupled(new MetaWriteReq).flip
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val resp = Vec.fill(conf.ways){(new MetaData).asOutput}
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}
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val rst_cnt = Reg(init=UInt(0, log2Up(conf.sets+1)))
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