riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Make data RAMs 1RW instead of 1R1W

Browse Source
This commit is contained in:
Andrew Waterman 2014-12-15 17:36:17 -08:00
parent 6a8b66231c
commit d04da83f96
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
uncore/src/main/scala/cache.scala
View File

@ -216,10 +216,13 @@ class L2DataArray extends L2HellaCacheModule {
val wmask = FillInterleaved(8, io.write.bits.wmask)
val resp = (0 until nWays).map { w =>
val array = Mem(Bits(width=rowBits), nSets*refillCycles, seqRead = true)
val reg_raddr = Reg(UInt())
when (io.write.bits.way_en(w) && io.write.valid) {
array.write(waddr, io.write.bits.data, wmask)
}.elsewhen (io.read.bits.way_en(w) && io.read.valid) {
reg_raddr := raddr
}
array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid))
array(reg_raddr)
}
io.resp.valid := ShiftRegister(io.read.fire(), 1)
io.resp.bits.id := ShiftRegister(io.read.bits.id, 1)