always merge Puts
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@ -173,7 +173,6 @@ abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgen
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require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
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val nSecondaryMisses = 4
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val enableGetMerging = false
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val enablePutMerging = true
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}
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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@ -709,11 +708,10 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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do_allocate &&
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ignt_q.io.enq.ready
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//TODO: mix Puts and PutBlocks
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val can_merge_iacq_put = ((Bool(enablePutMerging) &&
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(xact.isBuiltInType(Acquire.putType) &&
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io.iacq().isBuiltInType(Acquire.putType))) ||
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(xact.isBuiltInType(Acquire.putBlockType) &&
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io.iacq().isBuiltInType(Acquire.putBlockType))) &&
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val can_merge_iacq_put = ((xact.isBuiltInType(Acquire.putType) &&
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io.iacq().isBuiltInType(Acquire.putType)) ||
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(xact.isBuiltInType(Acquire.putBlockType) &&
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io.iacq().isBuiltInType(Acquire.putBlockType))) &&
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(xact_src === io.inner.acquire.bits.header.src) &&
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(xact.client_xact_id === io.iacq().client_xact_id) &&
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xact.conflicts(io.iacq()) &&
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