make sure ID width requirement in TL -> NASTI converter is correct
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@ -1422,12 +1422,10 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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MT_Q -> UInt(log2Up(tlDataBytes))))
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val dataBits = tlDataBits*tlDataBeats
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val dstIdBits = p(LNHeaderBits)
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require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
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require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
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require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NastiIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)
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require(tlClientXactIdBits <= nastiXIdBits, "NastiIO converter is going truncate tags: " + tlClientXactIdBits + " > " + nastiXIdBits)
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val dst_off = dstIdBits + tlClientXactIdBits
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val has_data = io.tl.acquire.bits.hasData()
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val is_subblock = io.tl.acquire.bits.isSubBlockType()
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