move ReorderQueue to utils.scala
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parent
0fe16ac1c0
commit
993ed86198
@ -1241,47 +1241,6 @@ trait HasDataBeatCounters {
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}
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}
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class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
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val data = dType.cloneType
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val tag = UInt(width = tagWidth)
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override def cloneType =
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new ReorderQueueWrite(dType, tagWidth).asInstanceOf[this.type]
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}
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class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
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extends Module {
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val io = new Bundle {
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val enq = Decoupled(new ReorderQueueWrite(dType, tagWidth)).flip
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val deq = new Bundle {
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val valid = Bool(INPUT)
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val tag = UInt(INPUT, tagWidth)
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val data = dType.cloneType.asOutput
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}
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val full = Bool(OUTPUT)
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}
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val roq_data = Reg(Vec(dType.cloneType, size))
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val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
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val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
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val roq_enq_addr = PriorityEncoder(roq_free)
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val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))
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io.enq.ready := roq_free.reduce(_ || _)
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io.deq.data := roq_data(roq_deq_addr)
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when (io.enq.valid && io.enq.ready) {
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roq_data(roq_enq_addr) := io.enq.bits.data
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roq_tags(roq_enq_addr) := io.enq.bits.tag
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roq_free(roq_enq_addr) := Bool(false)
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}
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when (io.deq.valid) {
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roq_free(roq_deq_addr) := Bool(true)
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}
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}
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class ClientTileLinkIOUnwrapperInfo extends Bundle {
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val voluntary = Bool()
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val builtin = Bool()
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@ -104,3 +104,44 @@ object FlowThroughSerializer {
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fs.io.out
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}
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}
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class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
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val data = dType.cloneType
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val tag = UInt(width = tagWidth)
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override def cloneType =
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new ReorderQueueWrite(dType, tagWidth).asInstanceOf[this.type]
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}
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class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
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extends Module {
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val io = new Bundle {
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val enq = Decoupled(new ReorderQueueWrite(dType, tagWidth)).flip
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val deq = new Bundle {
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val valid = Bool(INPUT)
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val tag = UInt(INPUT, tagWidth)
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val data = dType.cloneType.asOutput
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}
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val full = Bool(OUTPUT)
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}
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val roq_data = Reg(Vec(dType.cloneType, size))
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val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
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val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
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val roq_enq_addr = PriorityEncoder(roq_free)
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val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))
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io.enq.ready := roq_free.reduce(_ || _)
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io.deq.data := roq_data(roq_deq_addr)
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when (io.enq.valid && io.enq.ready) {
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roq_data(roq_enq_addr) := io.enq.bits.data
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roq_tags(roq_enq_addr) := io.enq.bits.tag
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roq_free(roq_enq_addr) := Bool(false)
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}
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when (io.deq.valid) {
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roq_free(roq_deq_addr) := Bool(true)
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}
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}
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