TileLinkNarrower should do nothing if interfaces are the same width
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83df05cb6a
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@ -1488,88 +1488,90 @@ class TileLinkIONarrower(factor: Int) extends TLModule {
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val out = Bundle(new ClientUncachedTileLinkIO)(outerParams)
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}
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val iacq = io.in.acquire.bits
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val ognt = io.out.grant.bits
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if (factor > 1) {
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val iacq = io.in.acquire.bits
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val ognt = io.out.grant.bits
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val stretch = iacq.a_type === Acquire.putBlockType
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val shrink = iacq.a_type === Acquire.getBlockType
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val stretch = iacq.a_type === Acquire.putBlockType
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val shrink = iacq.a_type === Acquire.getBlockType
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val acq_data_buffer = Reg(UInt(width = tlDataBits))
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val acq_wmask_buffer = Reg(UInt(width = tlWriteMaskBits))
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val acq_client_id = Reg(iacq.client_xact_id)
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val acq_addr_block = Reg(iacq.addr_block)
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val acq_addr_beat = Reg(iacq.addr_beat)
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val oacq_ctr = Counter(factor)
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val acq_data_buffer = Reg(UInt(width = tlDataBits))
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val acq_wmask_buffer = Reg(UInt(width = tlWriteMaskBits))
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val acq_client_id = Reg(iacq.client_xact_id)
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val acq_addr_block = Reg(iacq.addr_block)
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val acq_addr_beat = Reg(iacq.addr_beat)
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val oacq_ctr = Counter(factor)
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val get_block_acquire = GetBlock(
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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alloc = iacq.allocate())
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val get_block_acquire = GetBlock(
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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alloc = iacq.allocate())
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val put_block_acquire = PutBlock(
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client_xact_id = acq_client_id,
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addr_block = acq_addr_block,
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addr_beat = if (factor > 1)
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Cat(acq_addr_beat, oacq_ctr.value)
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else acq_addr_beat,
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data = acq_data_buffer(outerDataBits - 1, 0),
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wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))
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val put_block_acquire = PutBlock(
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client_xact_id = acq_client_id,
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addr_block = acq_addr_block,
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addr_beat = if (factor > 1)
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Cat(acq_addr_beat, oacq_ctr.value)
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else acq_addr_beat,
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data = acq_data_buffer(outerDataBits - 1, 0),
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wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))
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val sending_put = Reg(init = Bool(false))
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val sending_put = Reg(init = Bool(false))
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io.out.acquire.bits := MuxBundle(iacq, Seq(
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(sending_put, put_block_acquire),
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(shrink, get_block_acquire)))
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io.out.acquire.valid := sending_put || (io.in.acquire.valid && !stretch)
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io.in.acquire.ready := !sending_put && (stretch || io.out.acquire.ready)
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io.out.acquire.bits := MuxBundle(iacq, Seq(
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(sending_put, put_block_acquire),
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(shrink, get_block_acquire)))
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io.out.acquire.valid := sending_put || (io.in.acquire.valid && !stretch)
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io.in.acquire.ready := !sending_put && (stretch || io.out.acquire.ready)
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when (io.in.acquire.fire() && stretch) {
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acq_data_buffer := iacq.data
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acq_wmask_buffer := iacq.wmask()
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acq_client_id := iacq.client_xact_id
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acq_addr_block := iacq.addr_block
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acq_addr_beat := iacq.addr_beat
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sending_put := Bool(true)
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}
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when (sending_put && io.out.acquire.ready) {
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acq_data_buffer := acq_data_buffer >> outerDataBits
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acq_wmask_buffer := acq_wmask_buffer >> outerWriteMaskBits
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when (oacq_ctr.inc()) { sending_put := Bool(false) }
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}
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val ognt_block = ognt.hasMultibeatData()
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val gnt_data_buffer = Reg(Vec(factor, UInt(width = outerDataBits)))
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val gnt_client_id = Reg(ognt.client_xact_id)
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val gnt_manager_id = Reg(ognt.manager_xact_id)
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val ignt_ctr = Counter(tlDataBeats)
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val ognt_ctr = Counter(factor)
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val sending_get = Reg(init = Bool(false))
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val get_block_grant = Grant(
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is_builtin_type = Bool(true),
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g_type = Grant.getDataBlockType,
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client_xact_id = gnt_client_id,
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manager_xact_id = gnt_manager_id,
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addr_beat = ignt_ctr.value,
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data = gnt_data_buffer.toBits)
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io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block)
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io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready)
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io.in.grant.bits := Mux(sending_get, get_block_grant, ognt)
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when (io.out.grant.valid && ognt_block && !sending_get) {
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gnt_data_buffer(ognt_ctr.value) := ognt.data
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when (ognt_ctr.inc()) {
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gnt_client_id := ognt.client_xact_id
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gnt_manager_id := ognt.manager_xact_id
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sending_get := Bool(true)
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when (io.in.acquire.fire() && stretch) {
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acq_data_buffer := iacq.data
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acq_wmask_buffer := iacq.wmask()
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acq_client_id := iacq.client_xact_id
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acq_addr_block := iacq.addr_block
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acq_addr_beat := iacq.addr_beat
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sending_put := Bool(true)
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}
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}
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when (io.in.grant.ready && sending_get) {
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ignt_ctr.inc()
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sending_get := Bool(false)
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}
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when (sending_put && io.out.acquire.ready) {
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acq_data_buffer := acq_data_buffer >> outerDataBits
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acq_wmask_buffer := acq_wmask_buffer >> outerWriteMaskBits
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when (oacq_ctr.inc()) { sending_put := Bool(false) }
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}
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val ognt_block = ognt.hasMultibeatData()
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val gnt_data_buffer = Reg(Vec(factor, UInt(width = outerDataBits)))
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val gnt_client_id = Reg(ognt.client_xact_id)
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val gnt_manager_id = Reg(ognt.manager_xact_id)
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val ignt_ctr = Counter(tlDataBeats)
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val ognt_ctr = Counter(factor)
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val sending_get = Reg(init = Bool(false))
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val get_block_grant = Grant(
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is_builtin_type = Bool(true),
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g_type = Grant.getDataBlockType,
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client_xact_id = gnt_client_id,
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manager_xact_id = gnt_manager_id,
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addr_beat = ignt_ctr.value,
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data = gnt_data_buffer.toBits)
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io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block)
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io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready)
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io.in.grant.bits := Mux(sending_get, get_block_grant, ognt)
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when (io.out.grant.valid && ognt_block && !sending_get) {
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gnt_data_buffer(ognt_ctr.value) := ognt.data
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when (ognt_ctr.inc()) {
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gnt_client_id := ognt.client_xact_id
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gnt_manager_id := ognt.manager_xact_id
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sending_get := Bool(true)
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}
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}
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when (io.in.grant.ready && sending_get) {
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ignt_ctr.inc()
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sending_get := Bool(false)
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}
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} else { io.out <> io.in }
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}
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