nasti converters, hub bugfix
This commit is contained in:
parent
c202449e34
commit
f3a838cedf
@ -111,6 +111,8 @@ class L2BroadcastHub extends ManagerCoherenceAgent
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io.outer.acquire.bits.data := MuxLookup(outer_data_ptr.loc, io.irel().data, Array(
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inStoreQueue -> sdq(outer_data_ptr.idx),
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inVolWBQueue -> vwbdq(outer_data_ptr.idx)))
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io.outer.acquire.bits.union := Cat(Fill(outer_arb.io.out.acquire.bits.union(1), io.outer.acquire.bits.tlWriteMaskBits),
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outer_arb.io.out.acquire.bits.union(0))
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io.outer <> outer_arb.io.out
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// Update SDQ valid bits
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@ -641,7 +641,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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// Provide a single ALU per tracker to merge Puts and AMOs with data being
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// refilled, written back, or extant in the cache
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val amoalu = Module(new AMOALU)
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amoalu.io.addr := xact.addr()
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amoalu.io.addr := xact.full_addr()
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amoalu.io.cmd := xact.op_code()
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amoalu.io.typ := xact.op_size()
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amoalu.io.lhs := io.data.resp.bits.data // default, overwritten by calls to mergeData
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@ -2,24 +2,43 @@
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package uncore
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import Chisel._
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import scala.math.max
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case object NASTIDataBits extends Field[Int]
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case object NASTIAddrBits extends Field[Int]
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case object NASTIReadIdBits extends Field[Int]
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case object NASTIWriteIdBits extends Field[Int]
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case object NASTIIdBits extends Field[Int]
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trait NASTIParameters extends UsesParameters {
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val dataBits = params(NASTIDataBits)
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val strobeBits = dataBits / 8
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val addrBits = params(NASTIAddrBits)
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val widBits = params(NASTIWriteIdBits)
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val ridBits = params(NASTIReadIdBits)
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val userBits = 32
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val awUserBits = userBits
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val wUserBits = userBits
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val bUserBits = userBits
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val arUserBits = userBits
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val rUserBits = userBits
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val nastiXDataBits = params(NASTIDataBits)
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val nastiWStrobeBits = nastiXDataBits / 8
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val nastiXAddrBits = params(NASTIAddrBits)
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val nastiWIdBits = params(NASTIIdBits)
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val nastiRIdBits = params(NASTIIdBits)
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val nastiXIdBits = max(nastiWIdBits, nastiRIdBits)
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val nastiXUserBits = 1
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val nastiAWUserBits = nastiXUserBits
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val nastiWUserBits = nastiXUserBits
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val nastiBUserBits = nastiXUserBits
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val nastiARUserBits = nastiXUserBits
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val nastiRUserBits = nastiXUserBits
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val nastiXLenBits = 8
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val nastiXSizeBits = 3
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val nastiXBurstBits = 2
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val nastiXCacheBits = 4
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val nastiXProtBits = 3
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val nastiXQosBits = 4
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val nastiXRegionBits = 4
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val nastiXRespBits = 2
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def bytesToXSize(bytes: UInt) = MuxLookup(bytes, UInt("b111"), Array(
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UInt(1) -> UInt(0),
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UInt(2) -> UInt(1),
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UInt(4) -> UInt(2),
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UInt(8) -> UInt(3),
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UInt(16) -> UInt(4),
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UInt(32) -> UInt(5),
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UInt(64) -> UInt(6),
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UInt(128) -> UInt(7)))
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}
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abstract class NASTIBundle extends Bundle with NASTIParameters
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@ -30,60 +49,247 @@ trait NASTIMasterToSlaveChannel extends NASTIChannel
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trait NASTISlaveToMasterChannel extends NASTIChannel
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class NASTIMasterIO extends Bundle {
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val writeAddress = Decoupled(new NASTIaw)
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val writeData = Decoupled(new NASTIw)
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val writeResponse = Decoupled(new NASTIb).flip
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val readAddress = Decoupled(new NASTIar)
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val readData = Decoupled(new NASTIr).flip
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val aw = Decoupled(new NASTIWriteAddressChannel)
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val w = Decoupled(new NASTIWriteDataChannel)
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val b = Decoupled(new NASTIWriteResponseChannel).flip
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val ar = Decoupled(new NASTIReadAddressChannel)
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val r = Decoupled(new NASTIReadDataChannel).flip
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}
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class NASTISlaveIO extends NASTIMasterIO { flip() }
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class NASTIaw extends NASTIMasterToSlaveChannel {
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val awID = UInt(width = widBits)
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val awAddr = UInt(width = addrBits)
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val awLen = UInt(width = 8)
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val awSize = UInt(width = 3)
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val awBurst = UInt(width = 2)
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val awCache = UInt(width = 4)
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val awProt = UInt(width = 3)
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val awQOS = UInt(width = 4)
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val awRegion = UInt(width = 4)
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val awLock = Bool()
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val awUser = UInt(width = awUserBits)
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trait HasNASTIMetadata extends NASTIBundle {
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val addr = UInt(width = nastiXAddrBits)
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val len = UInt(width = nastiXLenBits)
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val size = UInt(width = nastiXSizeBits)
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val burst = UInt(width = nastiXBurstBits)
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val lock = Bool()
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val cache = UInt(width = nastiXCacheBits)
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val prot = UInt(width = nastiXProtBits)
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val qos = UInt(width = nastiXQosBits)
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val region = UInt(width = nastiXRegionBits)
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}
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class NASTIw extends NASTIMasterToSlaveChannel {
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val wData = UInt(width = dataBits)
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val wStrb = UInt(width = strobeBits)
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val wUser = UInt(width = wUserBits)
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val wLast = Bool()
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trait HasNASTIData extends NASTIBundle {
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val data = UInt(width = nastiXDataBits)
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val last = Bool()
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}
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class NASTIb extends NASTISlaveToMasterChannel {
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val bID = UInt(width = widBits)
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val bResp = UInt(width = 2)
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val bUser = UInt(width = bUserBits)
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class NASTIAddressChannel extends NASTIMasterToSlaveChannel with HasNASTIMetadata
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class NASTIResponseChannel extends NASTISlaveToMasterChannel {
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val resp = UInt(width = nastiXRespBits)
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}
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class NASTIar extends NASTIMasterToSlaveChannel {
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val arID = UInt(width = ridBits)
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val arAddr = UInt(width = addrBits)
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val arLen = UInt(width = 8)
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val arSize = UInt(width = 3)
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val arBurst = UInt(width = 2)
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val arCache = UInt(width = 4)
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val arQOS = UInt(width = 3)
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val arRegion = UInt(width = 4)
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val arProt = UInt(width = 4)
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val arLock = Bool()
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val arUser = UInt(width = arUserBits)
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class NASTIWriteAddressChannel extends NASTIAddressChannel {
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val id = UInt(width = nastiWIdBits)
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val user = UInt(width = nastiAWUserBits)
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}
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class NASTIr extends NASTISlaveToMasterChannel {
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val rID = UInt(width = ridBits)
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val rData = UInt(width = dataBits)
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val rResp = UInt(width = 2)
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val rUser = UInt(width = rUserBits)
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val rLast = Bool()
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class NASTIWriteDataChannel extends NASTIMasterToSlaveChannel with HasNASTIData {
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val strb = UInt(width = nastiWStrobeBits)
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val user = UInt(width = nastiWUserBits)
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}
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class NASTIWriteResponseChannel extends NASTIResponseChannel {
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val id = UInt(width = nastiWIdBits)
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val user = UInt(width = nastiBUserBits)
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}
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class NASTIReadAddressChannel extends NASTIAddressChannel {
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val id = UInt(width = nastiRIdBits)
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val user = UInt(width = nastiARUserBits)
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}
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class NASTIReadDataChannel extends NASTIResponseChannel with HasNASTIData {
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val id = UInt(width = nastiRIdBits)
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val user = UInt(width = nastiRUserBits)
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}
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class MemIONASTISlaveIOConverter extends MIFModule with NASTIParameters {
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val io = new Bundle {
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val nasti = new NASTISlaveIO
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val mem = new MemIO
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}
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require(mifDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree")
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val (mif_cnt_out, mif_wrap_out) = Counter(io.mem.resp.fire(), mifDataBeats)
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io.mem.req_cmd.bits.addr := Mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) >>
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UInt(params(CacheBlockOffsetBits))
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io.mem.req_cmd.bits.tag := Mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id)
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io.mem.req_cmd.bits.rw := io.nasti.aw.valid
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io.mem.req_cmd.valid := (io.nasti.aw.valid && io.nasti.b.ready) || io.nasti.ar.valid
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io.nasti.ar.ready := io.mem.req_cmd.ready && !io.nasti.aw.valid
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io.nasti.aw.ready := io.mem.req_cmd.ready && io.nasti.b.ready
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io.nasti.b.valid := io.nasti.aw.valid && io.mem.req_cmd.ready
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io.nasti.b.bits.id := io.nasti.aw.bits.id
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io.nasti.b.bits.resp := UInt(0)
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io.nasti.w.ready := io.mem.req_data.ready
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io.mem.req_data.valid := io.nasti.w.valid
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io.mem.req_data.bits.data := io.nasti.w.bits.data
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assert(!io.nasti.w.valid || io.nasti.w.bits.strb.andR, "MemIO must write full cache line")
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io.nasti.r.valid := io.mem.resp.valid
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io.nasti.r.bits.data := io.mem.resp.bits.data
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io.nasti.r.bits.last := mif_wrap_out
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io.nasti.r.bits.id := io.mem.resp.bits.tag
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io.nasti.r.bits.resp := UInt(0)
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io.mem.resp.ready := io.nasti.r.ready
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}
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class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters {
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val io = new Bundle {
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val tl = new ManagerTileLinkIO
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val nasti = new NASTIMasterIO
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}
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val dataBits = tlDataBits*tlDataBeats
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val dstIdBits = params(LNHeaderBits)
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require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
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require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
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require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NASTIMasterIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)
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io.tl.acquire.ready := Bool(false)
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io.tl.probe.valid := Bool(false)
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io.tl.release.ready := Bool(false)
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io.tl.finish.ready := Bool(true)
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io.nasti.b.ready := Bool(false)
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io.nasti.r.ready := Bool(false)
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io.nasti.ar.valid := Bool(false)
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io.nasti.aw.valid := Bool(false)
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io.nasti.w.valid := Bool(false)
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val dst_off = dstIdBits + tlClientXactIdBits
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val acq_has_data = io.tl.acquire.bits.hasData()
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val rel_has_data = io.tl.release.bits.hasData()
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val is_write = io.tl.release.valid || (io.tl.acquire.valid && acq_has_data)
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// Decompose outgoing TL Acquires into NASTI address and data channels
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val active_out = Reg(init=Bool(false))
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val cmd_sent_out = Reg(init=Bool(false))
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val tag_out = Reg(UInt(width = nastiXIdBits))
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val addr_out = Reg(UInt(width = nastiXAddrBits))
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val has_data = Reg(init=Bool(false))
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val data_from_rel = Reg(init=Bool(false))
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val (tl_cnt_out, tl_wrap_out) =
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Counter((io.tl.acquire.fire() && acq_has_data) ||
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(io.tl.release.fire() && rel_has_data), tlDataBeats)
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val tl_done_out = Reg(init=Bool(false))
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io.nasti.ar.bits.id := tag_out
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io.nasti.ar.bits.addr := addr_out
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io.nasti.ar.bits.len := Mux(has_data, UInt(tlDataBeats-1), UInt(0))
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io.nasti.ar.bits.size := UInt(log2Ceil(tlDataBits))
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io.nasti.ar.bits.burst := UInt("b01")
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io.nasti.ar.bits.lock := Bool(false)
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io.nasti.ar.bits.cache := UInt("b0000")
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io.nasti.ar.bits.prot := UInt("b000")
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io.nasti.ar.bits.qos := UInt("b0000")
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io.nasti.ar.bits.region := UInt("b0000")
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io.nasti.ar.bits.user := UInt(0)
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io.nasti.aw.bits := io.nasti.ar.bits
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io.nasti.w.bits.strb := Mux(data_from_rel, SInt(-1), io.tl.acquire.bits.wmask())
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io.nasti.w.bits.data := Mux(data_from_rel, io.tl.release.bits.data, io.tl.acquire.bits.data)
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io.nasti.w.bits.last := tl_wrap_out
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when(!active_out){
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io.tl.release.ready := io.nasti.w.ready
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io.tl.acquire.ready := io.nasti.w.ready && !io.tl.release.valid
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io.nasti.w.valid := (io.tl.release.valid && rel_has_data) ||
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(io.tl.acquire.valid && acq_has_data)
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when(io.nasti.w.ready && (io.tl.release.valid || io.tl.acquire.valid)) {
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active_out := (!is_write && !io.nasti.ar.ready) ||
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(is_write && !(io.nasti.aw.ready && io.nasti.w.ready)) ||
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(io.nasti.w.valid && Bool(tlDataBeats > 1))
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io.nasti.aw.valid := is_write
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io.nasti.ar.valid := !is_write
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cmd_sent_out := (!is_write && io.nasti.ar.ready) || (is_write && io.nasti.aw.ready)
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tl_done_out := tl_wrap_out
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when(io.tl.release.valid) {
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data_from_rel := Bool(true)
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io.nasti.w.bits.data := io.tl.release.bits.data
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io.nasti.w.bits.strb := SInt(-1)
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val tag = Cat(io.tl.release.bits.client_id,
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io.tl.release.bits.client_xact_id,
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io.tl.release.bits.isVoluntary())
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val addr = io.tl.release.bits.full_addr()
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io.nasti.aw.bits.id := tag
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io.nasti.aw.bits.addr := addr
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io.nasti.aw.bits.len := UInt(tlDataBeats-1)
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io.nasti.aw.bits.size := MT_Q
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tag_out := tag
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addr_out := addr
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has_data := rel_has_data
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} .elsewhen(io.tl.acquire.valid) {
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data_from_rel := Bool(false)
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io.nasti.w.bits.data := io.tl.acquire.bits.data
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io.nasti.w.bits.strb := io.tl.acquire.bits.wmask()
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val tag = Cat(io.tl.acquire.bits.client_id,
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io.tl.acquire.bits.client_xact_id,
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io.tl.acquire.bits.isBuiltInType())
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val addr = io.tl.acquire.bits.full_addr()
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when(is_write) {
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io.nasti.aw.bits.id := tag
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io.nasti.aw.bits.addr := addr
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io.nasti.aw.bits.len := Mux(io.tl.acquire.bits.isBuiltInType(Acquire.putBlockType),
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UInt(tlDataBeats-1), UInt(0))
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io.nasti.aw.bits.size := bytesToXSize(PopCount(io.tl.acquire.bits.wmask()))
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} .otherwise {
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io.nasti.ar.bits.id := tag
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io.nasti.ar.bits.addr := addr
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io.nasti.ar.bits.len := Mux(io.tl.acquire.bits.isBuiltInType(Acquire.getBlockType),
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UInt(tlDataBeats-1), UInt(0))
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io.nasti.ar.bits.size := io.tl.acquire.bits.op_size()
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}
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tag_out := tag
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addr_out := addr
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has_data := acq_has_data
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}
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}
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}
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when(active_out) {
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io.nasti.ar.valid := !cmd_sent_out && !has_data
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io.nasti.aw.valid := !cmd_sent_out && has_data
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cmd_sent_out := cmd_sent_out || io.nasti.ar.fire() || io.nasti.aw.fire()
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when(has_data && !tl_done_out) {
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when(data_from_rel) {
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io.tl.release.ready := io.nasti.w.ready
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io.nasti.w.valid := io.tl.release.valid
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} .otherwise {
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io.tl.acquire.ready := io.nasti.w.ready
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io.nasti.w.valid := io.tl.acquire.valid
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}
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}
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when(tl_wrap_out) { tl_done_out := Bool(true) }
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when(cmd_sent_out && (!has_data || tl_done_out)) { active_out := Bool(false) }
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}
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// Aggregate incoming NASTI responses into TL Grants
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val (tl_cnt_in, tl_wrap_in) = Counter(io.tl.grant.fire() && io.tl.grant.bits.hasMultibeatData(), tlDataBeats)
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val gnt_arb = Module(new Arbiter(new GrantToDst, 2))
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io.tl.grant <> gnt_arb.io.out
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gnt_arb.io.in(0).valid := io.nasti.r.valid
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io.nasti.r.ready := gnt_arb.io.in(0).ready
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gnt_arb.io.in(0).bits := Grant(
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dst = (if(dstIdBits > 0) io.nasti.r.bits.id(dst_off, tlClientXactIdBits + 1) else UInt(0)),
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is_builtin_type = io.nasti.r.bits.id(0),
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g_type = Mux(io.nasti.r.bits.id(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol
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client_xact_id = io.nasti.r.bits.id >> UInt(1),
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manager_xact_id = UInt(0),
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addr_beat = tl_cnt_in,
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data = io.nasti.r.bits.data)
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gnt_arb.io.in(1).valid := io.nasti.b.valid
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io.nasti.b.ready := gnt_arb.io.in(1).ready
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gnt_arb.io.in(1).bits := Grant(
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dst = (if(dstIdBits > 0) io.nasti.b.bits.id(dst_off, tlClientXactIdBits + 1) else UInt(0)),
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is_builtin_type = Bool(true),
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g_type = Mux(io.nasti.b.bits.id(0), Grant.voluntaryAckType, Grant.putAckType),
|
||||
client_xact_id = io.nasti.b.bits.id >> UInt(1),
|
||||
manager_xact_id = UInt(0))
|
||||
}
|
||||
|
@ -172,7 +172,7 @@ class Acquire extends ClientToManagerChannel
|
||||
/** Full, beat-sized writemask */
|
||||
def full_wmask(dummy: Int = 0) = FillInterleaved(8, wmask())
|
||||
/** Complete physical address for block, beat or operand */
|
||||
def addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, this.addr_byte())
|
||||
def full_addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, this.addr_byte())
|
||||
|
||||
// Other helper functions:
|
||||
/** Message type equality */
|
||||
@ -337,7 +337,7 @@ object GetBlock {
|
||||
a_type = Acquire.getBlockType,
|
||||
client_xact_id = client_xact_id,
|
||||
addr_block = addr_block,
|
||||
union = Cat(M_XRD, alloc))
|
||||
union = Cat(MT_Q, M_XRD, alloc))
|
||||
}
|
||||
}
|
||||
|
||||
@ -357,7 +357,7 @@ object GetPrefetch {
|
||||
client_xact_id = client_xact_id,
|
||||
addr_block = addr_block,
|
||||
addr_beat = UInt(0),
|
||||
union = Cat(M_XRD, Bool(true)))
|
||||
union = Cat(MT_Q, M_XRD, Bool(true)))
|
||||
}
|
||||
}
|
||||
|
||||
@ -548,6 +548,7 @@ class Release extends ClientToManagerChannel
|
||||
def hasMultibeatData(dummy: Int = 0) = Bool(tlDataBeats > 1) && tlCoh.releaseTypesWithData.contains(r_type)
|
||||
def isVoluntary(dummy: Int = 0) = voluntary
|
||||
def requiresAck(dummy: Int = 0) = !Bool(tlNetworkPreservesPointToPointOrdering)
|
||||
def full_addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, UInt(0, width = tlByteAddrBits))
|
||||
}
|
||||
|
||||
/** [[uncore.Release]] with an extra field stating its source id */
|
||||
|
Loading…
Reference in New Issue
Block a user