NetworkIOs no longer use thunks
This commit is contained in:
Henry Cook
parent
ee98cd8378
commit
1cac26fd76
@ -2,23 +2,23 @@ package uncore
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import Chisel._
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import scala.collection.mutable.Stack
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class PairedDataIO[M <: Data, D <: Data]()(m: => M, d: => D) extends Bundle {
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val meta = Decoupled(m)
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val data = Decoupled(d)
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override def clone = { new PairedDataIO()(m,d).asInstanceOf[this.type] }
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class PairedDataIO[M <: Data, D <: Data](mType: M, dType: D) extends Bundle {
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val meta = Decoupled(mType)
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val data = Decoupled(dType)
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override def clone = { new PairedDataIO(mType, dType).asInstanceOf[this.type] }
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}
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class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bundle {
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val in = Vec.fill(n){new PairedDataIO()(m,d)}.flip
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val out = new PairedDataIO()(m,d)
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val meta_chosen = Bits(OUTPUT, log2Up(n))
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val data_chosen = Bits(OUTPUT, log2Up(n))
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override def clone = { new PairedArbiterIO(n)(m,d).asInstanceOf[this.type] }
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class PairedArbiterIO[M <: Data, D <: Data](mType: M, dType: D, n: Int) extends Bundle {
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val in = Vec.fill(n){new PairedDataIO(mType, dType)}.flip
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val out = new PairedDataIO(mType, dType)
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val meta_chosen = UInt(OUTPUT, log2Up(n))
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val data_chosen = UInt(OUTPUT, log2Up(n))
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override def clone = { new PairedArbiterIO(mType, dType, n).asInstanceOf[this.type] }
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}
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class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) extends Module {
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class PairedLockingRRArbiter[M <: Data, D <: Data](mType: M, dType: D, n: Int, count: Int, needsLock: Option[M => Bool] = None) extends Module {
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require(isPow2(count))
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val io = new PairedArbiterIO(n)(meta,data)
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val io = new PairedArbiterIO(mType, dType, n)
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val locked = if(count > 1) Reg(init=Bool(false)) else Bool(false)
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val lockIdx = if(count > 1) Reg(init=UInt(n-1)) else UInt(n-1)
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val grant = List.fill(n)(Bool())
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@ -68,10 +68,10 @@ class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock
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when (io.out.meta.fire()) { last_grant := meta_chosen }
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}
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class PairedCrossbar[M <: Data, D <: Data](count: Int, needsLock: Option[PhysicalNetworkIO[M] => Bool] = None)(meta: => M, data: => D)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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class PairedCrossbar[M <: Data, D <: Data](mType: M, dType: D, count: Int, needsLock: Option[PhysicalNetworkIO[M] => Bool] = None)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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val io = new Bundle {
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val in = Vec.fill(conf.nEndpoints){new PairedDataIO()(new PhysicalNetworkIO()(meta),new PhysicalNetworkIO()(data))}.flip
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val out = Vec.fill(conf.nEndpoints){new PairedDataIO()(new PhysicalNetworkIO()(meta),new PhysicalNetworkIO()(data))}
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val in = Vec.fill(conf.nEndpoints){new PairedDataIO(new PhysicalNetworkIO(mType),new PhysicalNetworkIO(dType))}.flip
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val out = Vec.fill(conf.nEndpoints){new PairedDataIO(new PhysicalNetworkIO(mType),new PhysicalNetworkIO(dType))}
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}
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val metaRdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints){Bool()})
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@ -79,7 +79,7 @@ class PairedCrossbar[M <: Data, D <: Data](count: Int, needsLock: Option[Physica
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val rdyVecs = metaRdyVecs zip dataRdyVecs
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io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = Module(new PairedLockingRRArbiter(conf.nEndpoints, count, needsLock)(io.in(0).meta.bits.clone, io.in(0).data.bits.clone))
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val rrarb = Module(new PairedLockingRRArbiter(io.in(0).meta.bits.clone, io.in(0).data.bits.clone, conf.nEndpoints, count, needsLock))
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rrarb.io.in zip io.in zip rdys._1 zip rdys._2 map { case (((arb, in), meta_rdy), data_rdy) => {
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arb.meta.valid := in.meta.valid && (in.meta.bits.header.dst === UInt(i))
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arb.meta.bits := in.meta.bits
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@ -103,18 +103,18 @@ class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle
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val dst = UInt(width = conf.idBits)
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}
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class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val header = (new PhysicalHeader)
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val payload = data
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override def clone = { new PhysicalNetworkIO()(data).asInstanceOf[this.type] }
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class PhysicalNetworkIO[T <: Data](dType: T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val header = new PhysicalHeader
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val payload = dType.clone
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override def clone = { new PhysicalNetworkIO(dType).asInstanceOf[this.type] }
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}
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abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Module
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class BasicCrossbar[T <: Data](count: Int = 1)(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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class BasicCrossbar[T <: Data](dType: T, count: Int = 1)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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val io = new Bundle {
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val in = Vec.fill(conf.nEndpoints){Decoupled((new PhysicalNetworkIO){data})}.flip
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val out = Vec.fill(conf.nEndpoints){Decoupled((new PhysicalNetworkIO){data})}
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val in = Vec.fill(conf.nEndpoints){Decoupled(new PhysicalNetworkIO(dType))}.flip
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val out = Vec.fill(conf.nEndpoints){Decoupled(new PhysicalNetworkIO(dType))}
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}
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val rdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints)(Bool()))
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@ -148,7 +148,7 @@ class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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object FIFOedLogicalNetworkIOWrapper {
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def apply[T <: Data](in: DecoupledIO[T], src: UInt = UInt(0), dst: UInt = UInt(0))(implicit conf: LogicalNetworkConfiguration) = {
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val out = Decoupled((new LogicalNetworkIO){in.bits.clone}).asDirectionless
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val out = Decoupled(new LogicalNetworkIO(in.bits.clone)).asDirectionless
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out.valid := in.valid
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out.bits.payload := in.bits
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out.bits.header.dst := dst
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@ -168,8 +168,8 @@ object FIFOedLogicalNetworkIOUnwrapper {
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}
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}
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class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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class LogicalNetworkIO[T <: Data](dType: T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val header = new LogicalHeader
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val payload = data
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override def clone = { new LogicalNetworkIO()(data).asInstanceOf[this.type] }
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val payload = dType.clone
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override def clone = { new LogicalNetworkIO(dType).asInstanceOf[this.type] }
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}
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@ -91,32 +91,32 @@ class GrantAck(implicit val conf: TileLinkConfiguration) extends ClientSourcedMe
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trait DirectionalIO
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trait ClientSourcedIO extends DirectionalIO
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trait MasterSourcedIO extends DirectionalIO
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class ClientSourcedFIFOIO[T <: Data]()(data: => T) extends DecoupledIO(data) with ClientSourcedIO {
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override def clone = { new ClientSourcedFIFOIO()(data).asInstanceOf[this.type] }
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class ClientSourcedFIFOIO[T <: Data](dType: T) extends DecoupledIO(dType) with ClientSourcedIO {
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override def clone = { new ClientSourcedFIFOIO(dType).asInstanceOf[this.type] }
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}
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class ClientSourcedDataIO[M <: Data, D <: Data]()(meta: => M, data: => D) extends PairedDataIO()(meta,data) with ClientSourcedIO {
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override def clone = { new ClientSourcedDataIO()(meta,data).asInstanceOf[this.type] }
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class ClientSourcedDataIO[M <: Data, D <: Data](mType: M, dType: D) extends PairedDataIO(mType, dType) with ClientSourcedIO {
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override def clone = { new ClientSourcedDataIO(mType, dType).asInstanceOf[this.type] }
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}
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class MasterSourcedFIFOIO[T <: Data]()(data: => T) extends DecoupledIO(data) with MasterSourcedIO {
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class MasterSourcedFIFOIO[T <: Data](dType: T) extends DecoupledIO(dType) with MasterSourcedIO {
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flip()
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override def clone = { new MasterSourcedFIFOIO()(data).asInstanceOf[this.type] }
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override def clone = { new MasterSourcedFIFOIO(dType).asInstanceOf[this.type] }
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}
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class MasterSourcedDataIO[M <: Data, D <: Data]()(meta: => M, data: => D) extends PairedDataIO()(meta,data) with MasterSourcedIO {
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class MasterSourcedDataIO[M <: Data, D <: Data](mType: M, dType: D) extends PairedDataIO(mType, dType) with MasterSourcedIO {
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flip()
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override def clone = { new MasterSourcedDataIO()(meta,data).asInstanceOf[this.type] }
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override def clone = { new MasterSourcedDataIO(mType, dType).asInstanceOf[this.type] }
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}
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class UncachedTileLinkIO(implicit conf: TileLinkConfiguration) extends Bundle {
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implicit val ln = conf.ln
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val acquire = new ClientSourcedDataIO()(new LogicalNetworkIO()(new Acquire), new LogicalNetworkIO()(new AcquireData))
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val grant = new MasterSourcedFIFOIO()(new LogicalNetworkIO()(new Grant))
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val grant_ack = new ClientSourcedFIFOIO()(new LogicalNetworkIO()(new GrantAck))
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val acquire = new ClientSourcedDataIO(new LogicalNetworkIO(new Acquire), new LogicalNetworkIO(new AcquireData))
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val grant = new MasterSourcedFIFOIO(new LogicalNetworkIO(new Grant))
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val grant_ack = new ClientSourcedFIFOIO(new LogicalNetworkIO(new GrantAck))
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override def clone = { new UncachedTileLinkIO().asInstanceOf[this.type] }
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}
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class TileLinkIO(implicit conf: TileLinkConfiguration) extends UncachedTileLinkIO()(conf) {
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val probe = new MasterSourcedFIFOIO()(new LogicalNetworkIO()(new Probe))
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val release = new ClientSourcedDataIO()(new LogicalNetworkIO()(new Release), new LogicalNetworkIO()(new ReleaseData))
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val probe = new MasterSourcedFIFOIO(new LogicalNetworkIO(new Probe))
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val release = new ClientSourcedDataIO(new LogicalNetworkIO(new Release), new LogicalNetworkIO(new ReleaseData))
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override def clone = { new TileLinkIO().asInstanceOf[this.type] }
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}
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@ -131,7 +131,7 @@ abstract class UncachedTileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfigur
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val out = new UncachedTileLinkIO
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}
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def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
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val acq_arb = Module(new PairedLockingRRArbiter(n, REFILL_CYCLES, acqHasData _)((new LogicalNetworkIO){new Acquire},(new LogicalNetworkIO){new AcquireData}))
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val acq_arb = Module(new PairedLockingRRArbiter(new LogicalNetworkIO(new Acquire), new LogicalNetworkIO(new AcquireData), n, REFILL_CYCLES, acqHasData _))
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io.out.acquire <> acq_arb.io.out
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io.in.map(_.acquire).zipWithIndex.zip(acq_arb.io.in).map{ case ((req,id), arb) => {
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arb.data <> req.data
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@ -141,7 +141,7 @@ abstract class UncachedTileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfigur
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req.meta.ready := arb.meta.ready
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}}
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val grant_ack_arb = Module(new RRArbiter((new LogicalNetworkIO){new GrantAck},n))
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val grant_ack_arb = Module(new RRArbiter(new LogicalNetworkIO(new GrantAck), n))
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io.out.grant_ack <> grant_ack_arb.io.out
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grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
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@ -43,7 +43,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: L2CoherenceAgentConfiguration
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alloc_arb.io.out.ready := acquire.meta.valid && !block_acquires
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// Handle probe request generation
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val probe_arb = Module(new Arbiter((new LogicalNetworkIO){ new Probe }, trackerList.size))
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val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
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io.client.probe <> probe_arb.io.out
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probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.probe }
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@ -66,7 +66,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: L2CoherenceAgentConfiguration
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release.data.ready := trackerList.map(_.io.client.release.data.ready).reduce(_||_)
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// Reply to initial requestor
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val grant_arb = Module(new Arbiter((new LogicalNetworkIO){ new Grant }, trackerList.size))
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val grant_arb = Module(new Arbiter(new LogicalNetworkIO(new Grant), trackerList.size))
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io.client.grant <> grant_arb.io.out
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant }
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