riscv/rocket-chip
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Re-split mem resp tag and data queues

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This commit is contained in:
Henry Cook 2015-03-18 12:49:53 -07:00
parent 42aa4aa8ca
commit e325399c87
1 changed files with 14 additions and 4 deletions
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18
uncore/src/main/scala/memserdes.scala
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@ -544,11 +544,21 @@ class MemPipeIOMemIOConverter(numRequests: Int, refillCycles: Int) extends Modul
io.mem.req_data <> io.cpu.req_data
// Have separate queues to allow for different mem implementations
val resp_data_q = Module((new HellaQueue(numEntries)) { new MemResp })
resp_data_q.io.enq <> io.mem.resp
io.cpu.resp <> resp_data_q.io.deq
val resp_data_q = Module((new HellaQueue(numEntries)) { new MemData })
resp_data_q.io.enq.valid := io.mem.resp.valid
resp_data_q.io.enq.bits.data := io.mem.resp.bits.data
inc := resp_data_q.io.deq.fire()
val resp_tag_q = Module((new HellaQueue(numEntries)) { new MemTag })
resp_tag_q.io.enq.valid := io.mem.resp.valid
resp_tag_q.io.enq.bits.tag := io.mem.resp.bits.tag
io.cpu.resp.valid := resp_data_q.io.deq.valid && resp_tag_q.io.deq.valid
io.cpu.resp.bits.data := resp_data_q.io.deq.bits.data
io.cpu.resp.bits.tag := resp_tag_q.io.deq.bits.tag
resp_data_q.io.deq.ready := io.cpu.resp.ready
resp_tag_q.io.deq.ready := io.cpu.resp.ready
inc := resp_data_q.io.deq.fire() && resp_tag_q.io.deq.fire()
dec := io.mem.req_cmd.fire() && !io.mem.req_cmd.bits.rw
}