beginning of l2 cache
This commit is contained in:
Henry Cook
parent
5613dc7d1b
commit
39681303b8
431
uncore/src/main/scala/cache.scala
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431
uncore/src/main/scala/cache.scala
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@ -0,0 +1,431 @@
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package uncore
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import Chisel._
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abstract class CacheConfig {
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def sets: Int
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def ways: Int
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def tl: TileLinkConfiguration
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def as: AddressSpaceConfiguration
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def dm: Boolean
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def states: Int
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def lines: Int
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def tagbits: Int
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def idxbits: Int
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def offbits: Int
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def untagbits: Int
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def rowbits: Int
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def metabits: Int
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def statebits: Int
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}
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case class L2CacheConfig(val sets: Int, val ways: Int,
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nReleaseTransactions: Int, nAcquireTransactions: Int,
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nrpq: Int, nsdq: Int,
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val tl: TileLinkConfiguration,
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val as: AddressSpaceConfiguration) extends CacheConfig {
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def databits = tl.dataBits
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def states = tl.co.nMasterStates
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def lines = sets*ways
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def dm = ways == 1
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def offbits = 0
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def lineaddrbits = tl.addrBits
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def idxbits = log2Up(sets)
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def waybits = log2Up(ways)
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def untagbits = offbits + idxbits
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def tagbits = lineaddrbits - idxbits
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def databytes = databits/8
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def wordoffbits = log2Up(databytes)
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def rowbits = tl.dataBits
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def rowbytes = rowbits/8
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def rowoffbits = log2Up(rowbytes)
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def refillcycles = tl.dataBits/(rowbits)
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def statebits = log2Up(states)
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def metabits = statebits + tagbits
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require(states > 0)
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require(isPow2(sets))
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require(isPow2(ways)) // TODO: relax this
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require(rowbits == tl.dataBits) //TODO: relax this?
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}
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abstract trait CacheBundle extends Bundle {
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implicit val conf: CacheConfig
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override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
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}
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abstract trait L2CacheBundle extends Bundle {
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implicit val conf: L2CacheConfig
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override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
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}
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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def hit: Unit
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}
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class RandomReplacement(implicit val conf: CacheConfig) extends ReplacementPolicy {
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private val replace = Bool()
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replace := Bool(false)
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val lfsr = LFSR16(replace)
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def way = if(conf.dm) UInt(0) else lfsr(log2Up(conf.ways)-1,0)
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def miss = replace := Bool(true)
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def hit = {}
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}
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object L2MetaData {
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def apply(tag: Bits, state: UInt)(implicit conf: CacheConfig) = {
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val meta = new L2MetaData
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meta.state := state
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meta.tag := tag
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meta
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}
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}
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class L2MetaData(implicit val conf: CacheConfig) extends CacheBundle {
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val state = UInt(width = conf.statebits)
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val tag = Bits(width = conf.tagbits)
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}
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class L2MetaReadReq(implicit val conf: CacheConfig) extends CacheBundle {
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val idx = Bits(width = conf.idxbits)
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}
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class L2MetaWriteReq(implicit conf: CacheConfig) extends L2MetaReadReq()(conf) {
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val way_en = Bits(width = conf.ways)
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val data = new L2MetaData()
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}
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class L2MetaDataArray(implicit conf: CacheConfig) extends Module {
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implicit val tl = conf.tl
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val io = new Bundle {
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val read = Decoupled(new L2MetaReadReq).flip
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val write = Decoupled(new L2MetaWriteReq).flip
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val resp = Vec.fill(conf.ways){(new L2MetaData).asOutput}
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}
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val rst_cnt = Reg(init=UInt(0, log2Up(conf.sets+1)))
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val rst = rst_cnt < UInt(conf.sets)
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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val tags = Mem(UInt(width = conf.metabits*conf.ways), conf.sets, seqRead = true)
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when (rst || io.write.valid) {
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val addr = Mux(rst, rst_cnt, io.write.bits.idx)
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val data = Cat(Mux(rst, tl.co.newStateOnFlush, io.write.bits.data.state), io.write.bits.data.tag)
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val mask = Mux(rst, SInt(-1), io.write.bits.way_en)
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tags.write(addr, Fill(conf.ways, data), FillInterleaved(conf.metabits, mask))
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}
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val tag = tags(RegEnable(io.read.bits.idx, io.read.valid))
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for (w <- 0 until conf.ways) {
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val m = tag(conf.metabits*(w+1)-1, conf.metabits*w)
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io.resp(w).state := m >> UInt(conf.tagbits)
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io.resp(w).tag := m
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}
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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io.write.ready := !rst
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}
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class L2DataReadReq(implicit val conf: L2CacheConfig) extends L2CacheBundle {
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val way_en = Bits(width = conf.ways)
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val addr = Bits(width = conf.untagbits)
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}
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class L2DataWriteReq(implicit conf: L2CacheConfig) extends L2DataReadReq()(conf) {
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val wmask = Bits(width = conf.tl.writeMaskBits)
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val data = Bits(width = conf.rowbits)
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}
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class L2DataArray(implicit conf: L2CacheConfig) extends Module {
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val io = new Bundle {
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val read = Decoupled(new L2DataReadReq).flip
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val write = Decoupled(new L2DataWriteReq).flip
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val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.rowbits)}
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}
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val waddr = io.write.bits.addr >> UInt(conf.rowoffbits)
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val raddr = io.read.bits.addr >> UInt(conf.rowoffbits)
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val wmask = FillInterleaved(conf.databits, io.write.bits.wmask)
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for (w <- 0 until conf.ways) {
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val array = Mem(Bits(width=conf.rowbits), conf.sets*conf.refillcycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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io.resp(w) := array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid))
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}
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io.read.ready := Bool(true)
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io.write.ready := Bool(true)
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}
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class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceAgent()(conf.tl)
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{
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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// Create SHRs for outstanding transactions
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val nTrackers = conf.nReleaseTransactions + conf.nAcquireTransactions
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val trackerList = (0 until conf.nReleaseTransactions).map(id => Module(new L2VoluntaryReleaseTracker(id, bankId))) ++
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(conf.nReleaseTransactions until nTrackers).map(id => Module(new L2AcquireTracker(id, bankId)))
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// Propagate incoherence flags
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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// Handle acquire transaction initiation
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val acquire = io.client.acquire
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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val block_acquires = any_acquire_conflict
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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t.acquire.valid := alloc_arb.io.in(i).ready
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}
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acquire.ready := trackerList.map(_.io.client.acquire.ready).reduce(_||_) && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && !block_acquires
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// Handle probe request generation
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val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
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io.client.probe <> probe_arb.io.out
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probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.probe }
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// Handle releases, which might be voluntary and might have data
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val release = io.client.release
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val voluntary = co.isVoluntary(release.bits.payload)
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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val block_releases = Bool(false)
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
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//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
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val release_idx = Mux(voluntary, UInt(0), release.bits.payload.master_xact_id)
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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t.release.bits := release.bits
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t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
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}
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release.ready := Vec(trackerList.map(_.io.client.release.ready)).read(release_idx) && !block_releases
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// Reply to initial requestor
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val grant_arb = Module(new Arbiter(new LogicalNetworkIO(new Grant), trackerList.size))
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io.client.grant <> grant_arb.io.out
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant }
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// Free finished transactions
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val ack = io.client.grant_ack
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trackerList.map(_.io.client.grant_ack.valid := ack.valid)
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trackerList.map(_.io.client.grant_ack.bits := ack.bits)
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ack.ready := Bool(true)
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// Create an arbiter for the one memory port
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val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size))
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.master }
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io.master <> outer_arb.io.out
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}
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abstract class L2XactTracker()(implicit conf: L2CacheConfig) extends Module {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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val io = new Bundle {
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val client = (new TileLinkIO).flip
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val master = new UncachedTileLinkIO
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val tile_incoherent = Bits(INPUT, ln.nClients)
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val has_acquire_conflict = Bool(OUTPUT)
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val has_release_conflict = Bool(OUTPUT)
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}
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val c_acq = io.client.acquire.bits
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val c_rel = io.client.release.bits
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val c_gnt = io.client.grant.bits
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val c_ack = io.client.grant_ack.bits
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val m_gnt = io.master.grant.bits
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}
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class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: L2CacheConfig) extends L2XactTracker()(conf) {
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val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_idle)
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val xact = Reg{ new Release }
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val init_client_id = Reg(init=UInt(0, width = log2Up(ln.nClients)))
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val incoming_rel = io.client.release.bits
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io.has_acquire_conflict := Bool(false)
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, incoming_rel.payload.addr) &&
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(state != s_idle)
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io.master.grant.ready := Bool(false)
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io.master.acquire.valid := Bool(false)
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io.master.acquire.bits.header.src := UInt(bankId)
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//io.master.acquire.bits.header.dst TODO
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io.master.acquire.bits.payload := Acquire(co.getUncachedWriteAcquireType,
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xact.addr,
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UInt(trackerId),
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xact.data)
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io.client.acquire.ready := Bool(false)
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io.client.probe.valid := Bool(false)
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io.client.release.ready := Bool(false)
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io.client.grant.valid := Bool(false)
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io.client.grant.bits.header.src := UInt(bankId)
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io.client.grant.bits.header.dst := init_client_id
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io.client.grant.bits.payload := Grant(co.getGrantType(xact, UInt(0)),
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xact.client_xact_id,
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UInt(trackerId))
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switch (state) {
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is(s_idle) {
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io.client.release.ready := Bool(true)
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when( io.client.release.valid ) {
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xact := incoming_rel.payload
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init_client_id := incoming_rel.header.src
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state := Mux(co.messageHasData(incoming_rel.payload), s_mem, s_ack)
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}
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}
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is(s_mem) {
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io.master.acquire.valid := Bool(true)
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when(io.master.acquire.ready) { state := s_ack }
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}
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is(s_ack) {
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io.client.grant.valid := Bool(true)
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when(io.client.grant.ready) { state := s_idle }
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}
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}
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}
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class L2AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CacheConfig) extends L2XactTracker()(conf) {
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val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_busy :: Nil = Enum(UInt(), 6)
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val state = Reg(init=s_idle)
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val xact = Reg{ new Acquire }
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val init_client_id = Reg(init=UInt(0, width = log2Up(ln.nClients)))
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//TODO: Will need id reg for merged release xacts
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val init_sharer_cnt = Reg(init=UInt(0, width = log2Up(ln.nClients)))
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val release_count = if (ln.nClients == 1) UInt(0) else Reg(init=UInt(0, width = log2Up(ln.nClients)))
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val probe_flags = Reg(init=Bits(0, width = ln.nClients))
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val curr_p_id = PriorityEncoder(probe_flags)
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val pending_outer_write = co.messageHasData(xact)
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val pending_outer_read = co.needsOuterRead(xact.a_type, UInt(0))
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val outer_write_acq = Acquire(co.getUncachedWriteAcquireType,
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xact.addr, UInt(trackerId), xact.data)
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val outer_write_rel = Acquire(co.getUncachedWriteAcquireType,
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xact.addr, UInt(trackerId), c_rel.payload.data)
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val outer_read = Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId))
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val probe_initial_flags = Bits(width = ln.nClients)
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probe_initial_flags := Bits(0)
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if (ln.nClients > 1) {
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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val probe_self = Bool(true) //co.needsSelfProbe(io.client.acquire.bits.payload)
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val myflag = Mux(probe_self, Bits(0), UIntToOH(c_acq.header.src(log2Up(ln.nClients)-1,0)))
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probe_initial_flags := ~(io.tile_incoherent | myflag)
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}
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io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) && (state != s_idle)
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) && (state != s_idle)
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io.master.acquire.valid := Bool(false)
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io.master.acquire.bits.header.src := UInt(bankId)
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//io.master.acquire.bits.header.dst TODO
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io.master.acquire.bits.payload := outer_read
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io.master.grant.ready := io.client.grant.ready
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io.client.probe.valid := Bool(false)
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io.client.probe.bits.header.src := UInt(bankId)
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io.client.probe.bits.header.dst := curr_p_id
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io.client.probe.bits.payload := Probe(co.getProbeType(xact.a_type, UInt(0)),
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xact.addr,
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UInt(trackerId))
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val grant_type = co.getGrantType(xact.a_type, init_sharer_cnt)
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io.client.grant.valid := Bool(false)
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io.client.grant.bits.header.src := UInt(bankId)
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io.client.grant.bits.header.dst := init_client_id
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io.client.grant.bits.payload := Grant(grant_type,
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xact.client_xact_id,
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UInt(trackerId),
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m_gnt.payload.data)
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io.client.acquire.ready := Bool(false)
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io.client.release.ready := Bool(false)
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switch (state) {
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is(s_idle) {
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io.client.acquire.ready := Bool(true)
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val needs_outer_write = co.messageHasData(c_acq.payload)
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val needs_outer_read = co.needsOuterRead(c_acq.payload.a_type, UInt(0))
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when( io.client.acquire.valid ) {
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xact := c_acq.payload
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init_client_id := c_acq.header.src
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init_sharer_cnt := UInt(ln.nClients) // TODO: Broadcast only
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probe_flags := probe_initial_flags
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if(ln.nClients > 1) {
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release_count := PopCount(probe_initial_flags)
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state := Mux(probe_initial_flags.orR, s_probe,
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Mux(needs_outer_write, s_mem_write,
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Mux(needs_outer_read, s_mem_read, s_make_grant)))
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} else state := Mux(needs_outer_write, s_mem_write,
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Mux(needs_outer_read, s_mem_read, s_make_grant))
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}
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}
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is(s_probe) {
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// Generate probes
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io.client.probe.valid := probe_flags.orR
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when(io.client.probe.ready) {
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probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
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}
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// Handle releases, which may have data to be written back
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when(io.client.release.valid) {
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when(co.messageHasData(c_rel.payload)) {
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io.master.acquire.valid := Bool(true)
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io.master.acquire.bits.payload := outer_write_rel
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when(io.master.acquire.ready) {
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io.client.release.ready := Bool(true)
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if(ln.nClients > 1) release_count := release_count - UInt(1)
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when(release_count === UInt(1)) {
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state := Mux(pending_outer_write, s_mem_write,
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Mux(pending_outer_read, s_mem_read, s_make_grant))
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}
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}
|
||||
} .otherwise {
|
||||
io.client.release.ready := Bool(true)
|
||||
if(ln.nClients > 1) release_count := release_count - UInt(1)
|
||||
when(release_count === UInt(1)) {
|
||||
state := Mux(pending_outer_write, s_mem_write,
|
||||
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
is(s_mem_read) {
|
||||
io.master.acquire.valid := Bool(true)
|
||||
io.master.acquire.bits.payload := outer_read
|
||||
when(io.master.acquire.ready) {
|
||||
state := Mux(co.requiresAckForGrant(grant_type), s_busy, s_idle)
|
||||
}
|
||||
}
|
||||
is(s_mem_write) {
|
||||
io.master.acquire.valid := Bool(true)
|
||||
io.master.acquire.bits.payload := outer_write_acq
|
||||
when(io.master.acquire.ready) {
|
||||
state := Mux(pending_outer_read, s_mem_read, s_make_grant)
|
||||
}
|
||||
}
|
||||
is(s_make_grant) {
|
||||
io.client.grant.valid := Bool(true)
|
||||
when(io.client.grant.ready) {
|
||||
state := Mux(co.requiresAckForGrant(grant_type), s_busy, s_idle)
|
||||
}
|
||||
}
|
||||
is(s_busy) { // Nothing left to do but wait for transaction to complete
|
||||
when(io.master.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
|
||||
io.client.grant.valid := Bool(true)
|
||||
}
|
||||
when(io.client.grant_ack.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
|
||||
state := s_idle
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user