refactor NASTI to not use param
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47da284e56
commit
908922c1a4
@ -3,10 +3,10 @@ package uncore
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import Chisel._
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import junctions._
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class RTC(pcr_MTIME: Int) extends Module with HTIFParameters {
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val io = new NASTIIO
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class RTC(pcr_MTIME: Int)(implicit val p: Parameters) extends Module with HTIFParameters {
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val io = new NastiIO
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private val addrMap = params(NASTIAddrHashMap)
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private val addrMap = new AddrHashMap(params(NastiAddrMap))
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val addrTable = Vec.tabulate(nCores) { i =>
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UInt(addrMap(s"conf:csr$i").start + pcr_MTIME * scrDataBytes)
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@ -45,13 +45,13 @@ class RTC(pcr_MTIME: Int) extends Module with HTIFParameters {
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when (io.b.fire()) { send_acked(io.b.bits.id) := Bool(true) }
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io.aw.valid := sending_addr
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io.aw.bits := NASTIWriteAddressChannel(
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io.aw.bits := NastiWriteAddressChannel(
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id = coreId,
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addr = addrTable(coreId),
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size = UInt(log2Up(scrDataBytes)))
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io.w.valid := sending_data
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io.w.bits := NASTIWriteDataChannel(data = rtc)
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io.w.bits := NastiWriteDataChannel(data = rtc)
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io.b.ready := Bool(true)
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io.ar.valid := Bool(false)
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@ -1328,15 +1328,15 @@ class ClientTileLinkIOUnwrapper extends TLModule {
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io.in.probe.valid := Bool(false)
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}
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class NASTIIOTileLinkIOConverterInfo extends TLBundle {
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class NastiIOTileLinkIOConverterInfo extends TLBundle {
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val byteOff = UInt(width = tlByteAddrBits)
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val subblock = Bool()
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}
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class NASTIIOTileLinkIOConverter extends TLModule with NASTIParameters {
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class NastiIOTileLinkIOConverter(implicit val p: Parameters) extends TLModule with HasNastiParameters {
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val io = new Bundle {
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val tl = new ClientUncachedTileLinkIO().flip
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val nasti = new NASTIIO
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val nasti = new NastiIO
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}
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private def opSizeToXSize(ops: UInt) = MuxLookup(ops, UInt("b111"), Seq(
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@ -1352,7 +1352,7 @@ class NASTIIOTileLinkIOConverter extends TLModule with NASTIParameters {
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val dstIdBits = params(LNHeaderBits)
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require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
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require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
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require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NASTIIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)
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require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NastiIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)
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io.tl.acquire.ready := Bool(false)
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@ -1366,7 +1366,7 @@ class NASTIIOTileLinkIOConverter extends TLModule with NASTIParameters {
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val acq_has_data = io.tl.acquire.bits.hasData()
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val is_write = io.tl.acquire.valid && acq_has_data
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// Decompose outgoing TL Acquires into NASTI address and data channels
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// Decompose outgoing TL Acquires into Nasti address and data channels
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val active_out = Reg(init=Bool(false))
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val cmd_sent_out = Reg(init=Bool(false))
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val tag_out = Reg(UInt(width = nastiXIdBits))
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@ -1378,7 +1378,7 @@ class NASTIIOTileLinkIOConverter extends TLModule with NASTIParameters {
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val tl_done_out = Reg(init=Bool(false))
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val roq = Module(new ReorderQueue(
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new NASTIIOTileLinkIOConverterInfo,
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new NastiIOTileLinkIOConverterInfo,
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nastiRIdBits, tlMaxClientsPerPort))
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val (nasti_cnt_out, nasti_wrap_out) = Counter(
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@ -1391,13 +1391,13 @@ class NASTIIOTileLinkIOConverter extends TLModule with NASTIParameters {
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roq.io.deq.valid := io.nasti.r.fire() && (nasti_wrap_out || roq.io.deq.data.subblock)
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roq.io.deq.tag := io.nasti.r.bits.id
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io.nasti.ar.bits := NASTIReadAddressChannel(
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = tag_out,
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addr = addr_out,
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size = UInt(log2Ceil(tlDataBytes)),
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len = Mux(has_data, UInt(tlDataBeats - 1), UInt(0)))
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io.nasti.aw.bits := io.nasti.ar.bits
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io.nasti.w.bits := NASTIWriteDataChannel(
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io.nasti.w.bits := NastiWriteDataChannel(
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data = io.tl.acquire.bits.data,
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strb = io.tl.acquire.bits.wmask(),
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last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock))
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