fix wb bug
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05b5188ad9
commit
404773eb9f
@ -462,6 +462,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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val crel_wb_src = Reg(init = UInt(0, width = log2Up(nClients)))
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val crel_wb_g_type = Reg(init = UInt(0, width = co.grantTypeWidth))
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val wb_buffer = Reg{xact.data.clone}
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val addr_wb = Cat(xact_internal.meta.tag, xact.addr(untagBits-1,blockOffBits))
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val release_count = Reg(init = UInt(0, width = log2Up(nClients+1)))
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val pending_probes = Reg(init = co.dir().flush)
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@ -476,8 +477,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) &&
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(state != s_idle) //TODO: Also indexes
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) &&
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(state != s_idle) //TODO: Also indexes?
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io.has_release_conflict := (co.isCoherenceConflict(xact.addr, c_rel.payload.addr) ||
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co.isCoherenceConflict(addr_wb, c_rel.payload.addr)) &&
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(state != s_idle) //TODO: Also indexes?
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val next_coh_on_release = co.masterMetadataOnRelease(
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c_rel.payload,
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@ -488,7 +490,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
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xact_internal.meta.coh,
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c_gnt.header.dst)
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val addr_wb = Cat(xact_internal.meta.tag, xact.addr(untagBits-1,blockOffBits))
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val outer_write_acq = Bundle(UncachedWrite(xact.addr, UInt(trackerId), xact.data),
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{ case TLId => outerId })
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val outer_write_wb = Bundle(UncachedWrite(addr_wb, UInt(trackerId), wb_buffer),
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