separate queues for resp tag and data
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6e540825b2
commit
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@ -33,9 +33,9 @@ class MemReqCmd extends HasMemAddr with HasMemTag {
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val rw = Bool()
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}
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class MemResp extends HasMemData with HasMemTag
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class MemTag extends HasMemTag
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class MemData extends HasMemData
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class MemResp extends HasMemData with HasMemTag
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class MemIO extends Bundle {
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val req_cmd = Decoupled(new MemReqCmd)
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@ -543,9 +543,20 @@ class MemPipeIOMemIOConverter(numRequests: Int, refillCycles: Int) extends Modul
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io.mem.req_data <> io.cpu.req_data
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val resp_dataq = Module((new HellaQueue(numEntries)) { new MemResp })
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resp_dataq.io.enq <> io.mem.resp
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io.cpu.resp <> resp_dataq.io.deq
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// Have separate queues to allow for different mem implementations
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val resp_dataq = Module((new HellaQueue(numEntries)) { new MemData })
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resp_dataq.io.enq.valid := io.mem.resp.valid
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resp_dataq.io.enq.bits.data := io.mem.resp.bits.data
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val resp_tagq = Module((new HellaQueue(numEntries)) { new MemTag })
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resp_tagq.io.enq.valid := io.mem.resp.valid
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resp_tagq.io.enq.bits.tag := io.mem.resp.bits.tag
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io.cpu.resp.valid := resp_dataq.io.deq.valid && resp_tagq.io.deq.valid
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io.cpu.resp.bits.data := resp_dataq.io.deq.bits.data
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io.cpu.resp.bits.tag := resp_tagq.io.deq.bits.tag
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resp_dataq.io.deq.ready := io.cpu.resp.ready
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resp_tagq.io.deq.ready := io.cpu.resp.ready
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inc := resp_dataq.io.deq.fire()
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dec := io.mem.req_cmd.fire() && !io.mem.req_cmd.bits.rw
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