Chisel3 compatibility fixes
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@ -86,7 +86,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
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val rx_word_count = (rx_count >> log2Up(short_request_bits/w))
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val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
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val packet_ram_depth = long_request_bits/short_request_bits-1
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val packet_ram = Mem(Bits(width = short_request_bits), packet_ram_depth)
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val packet_ram = Mem(packet_ram_depth, Bits(width = short_request_bits))
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when (rx_word_done && io.host.in.ready) {
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packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in
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}
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